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📄 map72324.h

📁 st7 单片机模拟I2C软件包 对没有I2C总线的单片机需要I2C功能非常有用
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volatile unsigned char TBCSR    @0x43;	/* Control/Status Register           */
volatile unsigned char TBIC1HR  @0x44;	/* Input Capture 1 High              */
volatile unsigned char TBIC1LR  @0x45;	/* Input Capture 1 Low               */
volatile unsigned char TBOC1HR  @0x46;	/* Output Compare 1 High             */
volatile unsigned char TBOC1LR  @0x47;	/* Output Compare 1 Low              */
volatile unsigned char TBCHR    @0x48;	/* Counter High                      */
volatile unsigned char TBCLR    @0x49;	/* Counter Low                       */
volatile unsigned char TBACHR   @0x4a;	/* Alternate Counter High            */
volatile unsigned char TBACLR   @0x4b;	/* Alternate Counter Low             */
volatile unsigned char TBIC2HR  @0x4c;	/* Input Capture 2 High              */
volatile unsigned char TBIC2LR  @0x4d;	/* Input Capture 2 Low               */
volatile unsigned char TBOC2HR  @0x4e;	/* Output Compare 2 High             */
volatile unsigned char TBOC2LR  @0x4f;	/* Output Compare 2 Low              */

/*	SCI section */
volatile unsigned char SCISR    @0x50;	/* SCI Status Register               */
volatile unsigned char SCIDR    @0x51;	/* SCI Data Register                 */
volatile unsigned char SCIBRR   @0x52;	/* SCI Baud Rate Register            */
volatile unsigned char SCICR1   @0x53;	/* SCI Control Register 1            */
volatile unsigned char SCICR2   @0x54;	/* SCI Control Register 2            */
volatile unsigned char SCIERPR  @0x55;	/* SCI Receive Prescaler             */
volatile unsigned char SCIETPR  @0x57;	/* SCI Transmit Prescaler            */

/*	ADC section */
volatile unsigned char ADCCSR   @0x70;	/* ADC Control/Status Register       */
volatile unsigned char ADCDRH   @0x71;	/* ADC Data Register High            */
volatile unsigned char ADCDRL   @0x72;	/* ADC Data Register Low             */

#endif


/*****************************************************************************/
/***** H A R D W A R E   R E G I S T E R   B I T   D E F I N I T I O N S *****/
/*****************************************************************************/

/* General bit definition....................................................*/

#define ZERO        0x00
#define ONE         0x01
#define TWO         0x02
#define THREE       0x03
#define FOUR        0x04
#define FIVE        0x05
#define SIX         0x06
#define SEVEN       0x07
#define EIGHT       0x08
#define NINE        0x09
#define TEN         0x0A


/* Main Clock Control/Status Register                                        */
#define MCO        0x07        // Main Clock Out Selection
#define CP1        0x06        // CPU Clock Prescaler 1
#define CP0        0x05        // CPU Clock Prescaler 0
#define SMS        0x04        // Slow Mode Select
#define TB1        0x03        // Time Base Control 1  
#define TB0        0x02        // Time Base Control 0
#define OIE        0x01        // Oscillator Interrupt Enable
#define OIF        0x00        // Oscillator Interrupt Flag

/* MCC Beep Control register                                                 */
#define BC1        0x01        // Beep Control 1
#define BC0        0x00        // Beep Control 0

/*External Interrupt Control Register                                        */
#define IS11       0x07        // ei2 & ei3 sensitivity
#define IS10       0x06        // ei2 & ei3 sensitivity
#define IPB        0x05        // Interrupt Polarity For Port B
#define IS21       0x04        // ei0 & ei1 sensitivity
#define IS20       0x03        // ei0 & ei1 sensitivity
#define IPA        0x02        // Interrupt Polarity For Port A
#define TLIS       0x01        // Top Level Interrupt sensitivity
#define TLIE       0x00        // Top Level Interrupt enable

/* SPI Control Register bit definition                                       */
#define SPIE        0x07       // SPI interrupt enable
#define SPE         0x06       // SPI Output enable
#define SPR2        0x05       // SPI Divder by to Enable
#define MSTR        0x04       // SPI Master mode
#define CPOL        0x03       // SPI Clock Polarity
#define CPHA        0x02       // SPI Clock Phase

/* SPI status register bit definition                                        */
#define SPIF        0x07       // SPI data transfer flag
#define WCOL        0x06       // SPI write collision status
#define MODF        0x04       // SPI mode fault Flag
#define SSM         0x01       // SPI Slave Select Mode Selection
#define SSI         0x00       // SPI Slave Slect Internal Mode    

/* Timers A&B Control Register 1 bit definition                              */
#define ICIE        0x07       // Input capture interrupt enable                               
#define OCIE        0x06       // Output compare interrupt enable                            
#define TOIE        0x05       // Timer overflow interrupt enable
#define OLVL2       0x02       // Output level 2
#define IEDG1       0x01       // Input edge 1
#define OLVL1       0x00       // Ouput level 1

/* Timers A&B Control Register 2 bit definition                              */
#define OC1E        0x07       // Output compare 1 pin
#define OC2E        0x06       // Output compare 1 pin
#define OPM         0x05       // One pulse mode
#define PWM         0x04       // PWM Mode
#define IEDG2       0x01       // Input edge 2

/* Timer A&B Status register bit definition                                  */
#define ICF1        0x07       // Input capture 1 flag
#define OCF1        0x06       // Output compare 1 flag
#define TOF         0x05       // Timer overflow flag
#define ICF2        0x04       // Input capture 2 flag
#define OCF2        0x03       // Output compare 2 flag

/* SCI status register bit definition                                        */
#define TDRE        0x07       // Tansmit data register empty
#define TC          0x06       // Transmission complete
#define RDRF        0x05       // Received data ready flag
#define IDLE        0x04       // Idle line detect
#define _0R         0x03       // Overrun error
#define NF          0x02       // Noise flag
#define FE          0x01       // Framing error

/* SCI control register 1 bit definition                                     */
#define R8          0x07       // Receive data bit8
#define T8          0x06       // Transmit data bit8
#define M           0x04       // Word lenght
#define WAKE        0x03       // Wake-up method

/* SCI control register 2 bit definition                                     */
#define TIE         0x07       // Transmitter interrupt enable
#define TCIE        0x06       // Transmission complete interrupt enable
#define RIE         0x05       // Receiver interupt enable
#define ILIE        0x04       // Idle line interrupt enable
#define TE          0x03       // Transmitter enable
#define RE          0x02       // Receiver enable                         
#define RWU         0x01       // Receiver wake_up           
#define SBK         0x00       // Send break                  
 
/* ADC Control/Status Register bit definition                                */
#define COCO        0x07       // Conversion Complete
#define ADON        0x05       // A/D converter on   


/* General bit definition....................................................*/

#define ZERO        0x00
#define ONE         0x01
#define TWO         0x02
#define THREE       0x03
#define FOUR        0x04
#define FIVE        0x05
#define SIX         0x06
#define SEVEN       0x07
#define EIGHT       0x08
#define NINE        0x09
#define TEN         0x0A

/* SPI Control Register bit definition                                       */

#define SPIE        0x07        // SPI interrupt enable
#define SPE         0x06        // SPI Output enable
#define MSTR        0x04        // SPI Master mode

/* SPI status register bit definition                                        */                                    

#define SPIF        0x07        // SPI data transfer flag
#define WCOL        0x06        // SPI write collision status
#define MODF        0x04        // SPI mode fault Flag

/* I2C_SR1 register bit definition                                           */

#define RCPT	0x02		// Master in receiver mode if RCPT=1 
#define	ACK	0x01		// Acknowledge received if ACK=1
#define	M_SL	0x00		// I2C mode:master or slave

/* I2C_SR2 register bit definition                                           */

#define	AF 	0X01		// Acknowledge Failure
#define	BERR	0x00		// Bus Error

/* Timers A&B Control Register 1 bit definition                              */

#define ICIE        0x07        // Input capture interrupt enable                                    
#define OCIE        0x06        // Output compare interrupt enable                            
#define TOIE        0x05        // Timer overflow interrupt enable
#define OLVL2       0x02        // Output level 2
#define IEDG1       0x01        // Input edge 1
#define OLVL1       0x00        // Ouput level 1

/* Timers A&B Control Register 2 bit definition                              */

#define OC1E        0x07        // Output compare 1 pin
#define OC2E        0x06        // Output compare 1 pin
#define OPM         0x05        // One pulse mode
#define PWM         0x04        // PWM Mode
#define IEDG2       0x01        // Input edge 2

/* Timer A&B Status register bit definition                                  */

#define ICF1        0x07        // Input capture 1 flag
#define OCF1        0x06        // Output compare 1 flag
#define TOF         0x05        // Timer overflow flag
#define ICF2        0x04        // Input capture 2 flag
#define OCF2        0x03        // Output compare 2 flag

/* SCI status register bit definition                                        */

#define TDRE        0x07        // Tansmit data register empty
#define TC          0x06        // Transmission complete
#define RDRF        0x05        // Received data ready flag
#define IDLE        0x04        // Idle line detect
#define _0R         0x03        // Overrun error
#define NF          0x02        // Noise flag
#define FE          0x01        // Framing error

/* SCI control register 1 bit definition                                     */
#define R8          0x07        // Receive data bit8
#define T8          0x06        // Transmit data bit8
#define M           0x04        // Word lenght
#define WAKE        0x03        // Wake-up method

/* SCI control register 2 bit definition                                     */
#define TIE         0x07        // Transmitter interrupt enable
#define TCIE        0x06        // Transmission complete interrupt enable
#define RIE         0x05        // Receiver interupt enable
#define ILIE        0x04        // Idle line interrupt enable
#define TE          0x03        // Transmitter enable
#define RE          0x02        // Receiver enable                         
#define RWU         0x01        // Receiver wake_up           
#define SBK         0x00        // Send break                  
 
/* ADC Control/Status Register bit definition                                */  

#define COCO        0x07        // Conversion Complete
#define ADON        0x05        // A/D converter on





#endif

/************************ (c) 2003  ST Microelectronics *********************/

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