📄 map72324.h
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/********************** (c) 2003 ST Microelectronics *************************
PROJECT : ST72324
COMPILER : COSMIC And METROWERKS
MODULE : map72324.h
VERSION : V 1.0
CREATION DATE : 12/06/03
AUTHOR : Micro Controller Division Application Team
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DESCRIPTION : ST72324 Hardware Registers Mapping.
This file contains the description of the hardware registers of
the ST72324 microcontroller.
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MODIFICATIONS :
******************************************************************************/
#ifndef MAP72324_H
#define MAP72324_H
/* ***************************************
Peripherals Registers Definition
*************************************** */
#ifdef __HIWARE__
/* I/O ports registers */
#pragma DATA_SEG SHORT PORT_A
extern volatile unsigned char PADR; /* port A data register */
extern volatile unsigned char PADDR; /* port A data direction register */
extern volatile unsigned char PAOR; /* port A option register */
#pragma DATA_SEG SHORT PORT_B
extern volatile unsigned char PBDR; /* port B data register */
extern volatile unsigned char PBDDR; /* port B data direction register */
extern volatile unsigned char PBOR; /* port B option register */
#pragma DATA_SEG SHORT PORT_C
extern volatile unsigned char PCDR; /* port C data register */
extern volatile unsigned char PCDDR; /* port C data direction register */
extern volatile unsigned char PCOR; /* port C option register */
#pragma DATA_SEG SHORT PORT_D
extern volatile unsigned char PDDR; /* port D data register */
extern volatile unsigned char PDDDR; /* port D data direction register */
extern volatile unsigned char PDOR; /* port D option register */
#pragma DATA_SEG SHORT PORT_E
extern volatile unsigned char PEDR; /* port E data register */
extern volatile unsigned char PEDDR; /* port E data direction register */
extern volatile unsigned char PEOR; /* port E option register */
#pragma DATA_SEG SHORT PORT_F
extern volatile unsigned char PFDR; /* port F data register */
extern volatile unsigned char PFDDR; /* port F data direction register */
extern volatile unsigned char PFOR; /* port F option register */
#pragma DATA_SEG SHORT SPI
extern volatile unsigned char SPIDR; /* SPI Data Register */
extern volatile unsigned char SPICR; /* SPI Control Register */
extern volatile unsigned char SPISR; /* SPI Status Register */
#pragma DATA_SEG SHORT ITC
extern volatile unsigned char ITSPR0; /* Interrupt Sofware Priority
Register 0 */
extern volatile unsigned char ITSPR1; /* Interrupt Sofware Priority
Register 1 */
extern volatile unsigned char ITSPR2; /* Interrupt Sofware Priority
Register 2 */
extern volatile unsigned char ITSPR3; /* Interrupt Sofware Priority
Register 3 */
#pragma DATA_SEG SHORT EIC_R
extern volatile unsigned char EICR; /* External Interrupt control
Register */
#pragma DATA_SEG SHORT FCS_R
extern volatile unsigned char FCSR; /* Master Clock Control Status
Register */
#pragma DATA_SEG SHORT WDG
extern volatile unsigned char WDGCR; /* Watchdog control register */
#pragma DATA_SEG SHORT SICS_R
extern volatile unsigned char SICSR; /* System Integrity Control/Status
Register */
#pragma DATA_SEG SHORT MCC
extern volatile unsigned char MCCSR; /* Main Clock Control Status
Register */
extern volatile unsigned char MCCBCR; /* Main Clock Controller Beep
Control Register */
#pragma DATA_SEG SHORT TIMERA
extern volatile unsigned char TACR2; /* timer A control register 2 */
extern volatile unsigned char TACR1; /* timer A control register 1 */
extern volatile unsigned char TASR; /* timer A status register */
extern volatile unsigned char TAIC1HR; /* timer A input capture 1 high
register */
extern volatile unsigned char TAIC1LR; /* timer A input capture 1 low
register */
extern volatile unsigned char TAOC1HR; /* timer A output compare 1 high
register */
extern volatile unsigned char TAOC1LR; /* timer A output compare 1 low
register */
extern volatile unsigned char TACHR; /* timer A counter high register */
extern volatile unsigned char TACLR; /* timer A counter low register */
extern volatile unsigned char TAACHR; /* timer A alternate counter high
register */
extern volatile unsigned char TAACLR; /* timer A alternate counter low
register */
extern volatile unsigned char TAIC2HR; /* timer A input capture 2 high
register */
extern volatile unsigned char TAIC2LR; /* timer A input capture 2 low
register */
extern volatile unsigned char TAOC2HR; /* timer A output compare 2 high
register */
extern volatile unsigned char TAOC2LR; /* timer A output compare 2 low
register */
#pragma DATA_SEG SHORT TIMERB
extern volatile unsigned char TBCR2; /* timer B control register 2 */
extern volatile unsigned char TBCR1; /* timer B control register 1 */
extern volatile unsigned char TBSR; /* timer B status register */
extern volatile unsigned char TBIC1HR; /* timer B input capture 1 high
register */
extern volatile unsigned char TBIC1LR; /* timer B input capture 1 low
register */
extern volatile unsigned char TBOC1HR; /* timer B output compare 1 high
register */
extern volatile unsigned char TBOC1LR; /* timer B output compare 1 low
register */
extern volatile unsigned char TBCHR; /* timer B counter high register */
extern volatile unsigned char TBCLR; /* timer B counter low register */
extern volatile unsigned char TBACHR; /* timer B alternate counter high
register */
extern volatile unsigned char TBACLR; /* timer B alternate counter low
register */
extern volatile unsigned char TBIC2HR; /* timer B input capture 2 high
register */
extern volatile unsigned char TBIC2LR; /* timer B input capture 2 low
register */
extern volatile unsigned char TBOC2HR; /* timer B output compare 2 high
register */
extern volatile unsigned char TBOC2LR; /* timer B output compare 2 low
register */
#pragma DATA_SEG SHORT SCI
extern volatile unsigned char SCISR; /* SCI Status Register */
extern volatile unsigned char SCIDR; /* SCI Data Register */
extern volatile unsigned char SCIBRR; /* SCI Baud rate Register */
extern volatile unsigned char SCICR1; /* SCI Control Register 1 */
extern volatile unsigned char SCICR2; /* SCI Control Register 2 */
extern volatile unsigned char SCIERPR; /* SCI Extended receive prescaler
register */
extern volatile unsigned char RESERV; /* Reserved */
extern volatile unsigned char SCIETPR; /* SCI Extended transmit prescaler
register */
#pragma DATA_SEG SHORT ADC
extern volatile unsigned char ADCCSR; /* ADC Control Status Register */
extern volatile unsigned char ADCDRH; /* ADC Data High Register */
extern volatile unsigned char ADCDRL; /* ADC Data Low Register */
#pragma DATA_SEG DEFAULT
#endif
#ifdef __CSMC__
/* I/O ports registers */
volatile unsigned char PADR @0x00; /* Port A Data Register */
volatile unsigned char PADDR @0x01; /* Port A Data Direction */
volatile unsigned char PAOR @0x02; /* Port A Option register */
volatile unsigned char PBDR @0x03; /* Port B Data Register */
volatile unsigned char PBDDR @0x04; /* Port B Data Direction */
volatile unsigned char PBOR @0x05; /* Port B Option Register */
volatile unsigned char PCDR @0x06; /* Port C Data Register */
volatile unsigned char PCDDR @0x07; /* Port C Data Direction */
volatile unsigned char PCOR @0x08; /* Port C Option Register */
volatile unsigned char PDDR @0x09; /* Port D Data Register */
volatile unsigned char PDDDR @0x0a; /* Port D Data Direction */
volatile unsigned char PDOR @0x0b; /* Port D Option Register */
volatile unsigned char PEDR @0x0c; /* Port E Data Register */
volatile unsigned char PEDDR @0x0d; /* Port E Data Direction */
volatile unsigned char PEOR @0x0e; /* Port E Option Register */
volatile unsigned char PFDR @0x0f; /* Port F Data Register */
volatile unsigned char PFDDR @0x10; /* Port F Data Direction */
volatile unsigned char PFOR @0x11; /* Port F Option Register */
/* SPI section */
volatile unsigned char SPIDR @0x21; /* SPI Data Register */
volatile unsigned char SPICR @0x22; /* SPI Control Register */
volatile unsigned char SPICSR @0x23; /* SPI Control/Status Register */
/* ITC section */
volatile unsigned char ITSPR0 @0x24; /* Interrupt Software Priority Reg 0 */
volatile unsigned char ITSPR1 @0x25; /* Interrupt Software Priority Reg 1 */
volatile unsigned char ITSPR2 @0x26; /* Interrupt Software Priority Reg 2 */
volatile unsigned char ITSPR3 @0x27; /* Interrupt Software Priority Reg 3 */
volatile unsigned char EICR @0x28; /* External Interrupt Control Reg */
/* SYSTEM section */
volatile unsigned char FCSR @0x29; /* Flash Control/Status Register */
volatile unsigned char WDGCR @0x2a; /* Watchdog Control Register */
volatile unsigned char SICSR @0x2b; /* System Integrity Control/Status */
/* MCC section */
volatile unsigned char MCCSR @0x2c; /* Main Clock Control/Status Reg */
volatile unsigned char MCCBCR @0x2d; /* Main Clock Beep Control Register */
/* TIMER A section */
volatile unsigned char TACR2 @0x31; /* Control Register 2 */
volatile unsigned char TACR1 @0x32; /* Control Register 1 */
volatile unsigned char TACSR @0x33; /* Control/Status Register */
volatile unsigned char TAIC1HR @0x34; /* Input Capture 1 High */
volatile unsigned char TAIC1LR @0x35; /* Input Capture 1 Low */
volatile unsigned char TAOC1HR @0x36; /* Output Compare 1 High */
volatile unsigned char TAOC1LR @0x37; /* Output Compare 1 Low */
volatile unsigned char TACHR @0x38; /* Counter High */
volatile unsigned char TACLR @0x39; /* Counter Low */
volatile unsigned char TAACHR @0x3a; /* Alternate Counter High */
volatile unsigned char TAACLR @0x3b; /* Alternate Counter Low */
volatile unsigned char TAIC2HR @0x3c; /* Input Capture 2 High */
volatile unsigned char TAIC2LR @0x3d; /* Input Capture 2 Low */
volatile unsigned char TAOC2HR @0x3e; /* Output Compare 2 High */
volatile unsigned char TAOC2LR @0x3f; /* Output Compare 2 Low */
/* TIMER B section */
volatile unsigned char TBCR2 @0x41; /* Control Register 2 */
volatile unsigned char TBCR1 @0x42; /* Control Register 1 */
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