map72324.c

st7 单片机模拟I2C软件包 对没有I2C总线的单片机需要I2C功能非常有用

/********************** (c) 2003  ST Microelectronics **************************

PROJECT  : ST72324
COMPILER : COSMIC And METROWERK

MODULE  :  map72324.c
VERSION :  V 1.0

CREATION DATE :  12/06/03

AUTHOR : Micro Controller Division Application  Team

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DESCRIPTION : ST72324 Hardware Registers Mapping.

              This file contains the description of the hardware registers of
              the ST72324 microcontroller.
              
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MODIFICATIONS :

******************************************************************************/


/* ***************************************
   Peripherals Registers Definition
   *************************************** */

#ifdef __HIWARE__   
   

/* I/O ports registers */   
#pragma DATA_SEG SHORT PORT_A
   volatile unsigned char PADR;      /* port A data register                 */
   volatile unsigned char PADDR;     /* port A data direction register       */
   volatile unsigned char PAOR;      /* port A option register               */
  
#pragma DATA_SEG SHORT PORT_B  
   volatile unsigned char PBDR;      /* port B data register                 */
   volatile unsigned char PBDDR;     /* port B data direction register       */
   volatile unsigned char PBOR;      /* port B option register               */
  
#pragma DATA_SEG SHORT PORT_C
   volatile unsigned char PCDR;      /* port C data register                 */
   volatile unsigned char PCDDR;     /* port C data direction register       */
   volatile unsigned char PCOR;      /* port C option register               */

#pragma DATA_SEG SHORT PORT_D
   volatile unsigned char PDDR;      /* port D data register                 */
   volatile unsigned char PDDDR;     /* port D data direction register       */
   volatile unsigned char PDOR;      /* port D option register               */

#pragma DATA_SEG SHORT PORT_E
   volatile unsigned char PEDR;      /* port E data register                 */
   volatile unsigned char PEDDR;     /* port E data direction register       */
   volatile unsigned char PEOR;      /* port E option register               */

#pragma DATA_SEG SHORT PORT_F
   volatile unsigned char PFDR;      /* port F data register                 */
   volatile unsigned char PFDDR;     /* port F data direction register       */
   volatile unsigned char PFOR;      /* port F option register               */

#pragma DATA_SEG SHORT SPI
   volatile unsigned char SPIDR;     /* SPI Data Register                    */
   volatile unsigned char SPICR;     /* SPI Control Register                 */
   volatile unsigned char SPISR;     /* SPI Status Register                  */

#pragma DATA_SEG SHORT ITC
   volatile unsigned char ITSPR0;   /* Interrupt Sofware Priority Register 0 */
   volatile unsigned char ITSPR1;   /* Interrupt Sofware Priority Register 1 */
   volatile unsigned char ITSPR2;   /* Interrupt Sofware Priority Register 2 */
   volatile unsigned char ITSPR3;   /* Interrupt Sofware Priority Register 3 */
  
#pragma DATA_SEG SHORT EIC_R
   volatile unsigned char EICR;     /*  External Interrupt control Register  */

#pragma DATA_SEG SHORT FCS_R
   volatile unsigned char FCSR;      /* Master Clock Control Status Register */

#pragma DATA_SEG SHORT WDG
   volatile unsigned char WDGCR;     /* Watchdog control register            */

#pragma DATA_SEG SHORT SICS_R
   volatile unsigned char SICSR;     /* System Integrity Control/Status
                                        Register                             */

#pragma DATA_SEG SHORT MCC
   volatile unsigned char MCCSR;     /* Main Clock Control Status Register   */
   volatile unsigned char MCCBCR;    /* Main Clock Controller Beep Control 
                                        Register                             */
  
#pragma DATA_SEG SHORT TIMERA
   volatile unsigned char TACR2;     /* timer A control register 2           */
   volatile unsigned char TACR1;     /* timer A control register 1           */
   volatile unsigned char TASR;      /* timer A status register              */
   volatile unsigned char TAIC1HR;  /* timer A input capture 1 high register */
   volatile unsigned char TAIC1LR;   /* timer A input capture 1 low register */
   volatile unsigned char TAOC1HR;   /* timer A output compare 1 high
                                        register                             */
   volatile unsigned char TAOC1LR;   /* timer A output compare 1 low 
                                        register                             */
   volatile unsigned char TACHR;     /* timer A counter high register        */
   volatile unsigned char TACLR;     /* timer A counter low register         */
   volatile unsigned char TAACHR;    /* timer A alternate counter high 
                                        register                             */
   volatile unsigned char TAACLR;    /* timer A alternate counter low 
                                        register                             */
   volatile unsigned char TAIC2HR;   /* timer A input capture 2 high 
                                        register                             */
   volatile unsigned char TAIC2LR;   /* timer A input capture 2 low register */
   volatile unsigned char TAOC2HR;   /* timer A output compare 2 high
                                        register                             */
   volatile unsigned char TAOC2LR;  /* timer A output compare 2 low register */

#pragma DATA_SEG SHORT TIMERB  
   volatile unsigned char TBCR2;     /* timer B control register 2           */
   volatile unsigned char TBCR1;     /* timer B control register 1           */
   volatile unsigned char TBSR;      /* timer B status register              */
   volatile unsigned char TBIC1HR;  /* timer B input capture 1 high register */
   volatile unsigned char TBIC1LR;   /* timer B input capture 1 low register */
   volatile unsigned char TBOC1HR;   /* timer B output compare 1 high
                                        register                             */
   volatile unsigned char TBOC1LR;   /* timer B output compare 1 low 
                                        register                             */
   volatile unsigned char TBCHR;     /* timer B counter high register        */
   volatile unsigned char TBCLR;     /* timer B counter low register         */
   volatile unsigned char TBACHR;    /* timer B alternate counter high 
                                        register                             */
   volatile unsigned char TBACLR;    /* timer B alternate counter low 
                                        register                             */
   volatile unsigned char TBIC2HR;   /* timer B input capture 2 high 
                                        register                             */
   volatile unsigned char TBIC2LR;   /* timer B input capture 2 low register */
   volatile unsigned char TBOC2HR;   /* timer B output compare 2 high
                                        register                             */
   volatile unsigned char TBOC2LR;  /* timer B output compare 2 low register */        

#pragma DATA_SEG SHORT SCI
   volatile unsigned char SCISR;     /* SCI Status Register                  */
   volatile unsigned char SCIDR;     /* SCI Data Register                    */
   volatile unsigned char SCIBRR;    /* SCI Baud rate Register               */
   volatile unsigned char SCICR1;    /* SCI Control Register 1               */
   volatile unsigned char SCICR2;    /* SCI Control Register 2               */
   volatile unsigned char SCIERPR;   /* SCI Extended receive prescaler 
                                        register                             */
   volatile unsigned char RESERV;    /* Reserved                             */
   volatile unsigned char SCIETPR;   /* SCI Extended transmit prescaler 
                                        register                             */

#pragma DATA_SEG SHORT ADC
   volatile unsigned char ADCCSR;    /* ADC Control Status Register          */
   volatile unsigned char ADCDRH;    /* ADC Data High Register               */
   volatile unsigned char ADCDRL;    /* ADC Data Low  Register               */
                                                                                             
#endif
   


/*************************** (c) 2003  ST Microelectronics ****************************/