📄 msp430xg46x_tb_02.c
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//******************************************************************************
// MSP430xG46x Demo - Timer_B, Toggle P5.1, TBCCR0 Up Mode ISR, DCO SMCLK
//
// Description: Toggle P5.1 using software and TB_0 ISR. Timer_B is
// configured for up mode, thus the timer overflows when TBR counts to TBCCR0.
// In this example, TBCCR0 is loaded with 20000.
// ACLK = 32.768kHz, MCLK = SMCLK = TACLK = default DCO
//
// MSP430xG46x
// -----------------
// /|\| XIN|-
// | | | 32kHz
// --|RST XOUT|-
// | |
// | P5.1|-->LED
//
// K. Quiring/ M. Mitchell
// Texas Instruments Inc.
// October 2006
// Built with IAR Embedded Workbench Version: 3.41A
//******************************************************************************
#include <msp430xG46x.h>
void main(void)
{
volatile unsigned int i;
WDTCTL = WDTPW+WDTHOLD; // Stop WDT
FLL_CTL0 |= XCAP14PF; // Configure load caps
// Wait for xtal to stabilize
do
{
IFG1 &= ~OFIFG; // Clear OSCFault flag
for (i = 0x47FF; i > 0; i--); // Time for flag to set
}
while ((IFG1 & OFIFG)); // OSCFault flag still set?
P5DIR |= 0x002; // P5.1 output
TBCCTL0 = CCIE; // TBCCR0 interrupt enabled
TBCCR0 = 20000; //
TBCTL = TBSSEL_2+MC_1; // SMCLK, up mode
_BIS_SR(LPM0_bits + GIE); // CPU off, interrupts enabled
}
// Timer B0 interrupt service routine -- Toggle P5.1
#pragma vector=TIMERB0_VECTOR
__interrupt void Timer_B (void)
{
P5OUT ^= 0x02; // Toggle P5.1
}
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