📄 msp430xg46x_usart1_uart_9600.c
字号:
//******************************************************************************
// MSP430xG46x Demo - USART1, Ultra-Low Pwr UART 9600 Echo ISR, 32kHz ACLK
//
// Description: Echo a received character, RX ISR used. Normal mode is LPM3,
// USART1 RX interrupt triggers TX Echo.
// ACLK = UCLK1 = LFXT1 = 32768, MCLK = SMCLK = DCO~ 1048k
// Baud rate divider with 32768hz XTAL @9600 = 32768Hz/9600 = 3.41 (0003h 4Ah )
// //* An external watch crystal is required on XIN XOUT for ACLK *//
//
//
// MSP430xG461x
// -----------------
// /|\| XIN|-
// | | | 32kHz
// --|RST XOUT|-
// | |
// | P4.0|----------->
// | | 9600 - 8N1
// | P4.1|<-----------
//
//
// K. Quiring/ M. Mitchell
// Texas Instruments Inc.
// October 2006
// Built with IAR Embedded Workbench Version: 3.41A
//******************************************************************************
#include <msp430xG46x.h>
void main(void)
{
volatile unsigned int i;
WDTCTL = WDTPW + WDTHOLD; // Stop WDT
FLL_CTL0 |= XCAP14PF; // Configure load caps
do
{
IFG1 &= ~OFIFG; // Clear OSCFault flag
for (i = 0x47FF; i > 0; i--); // Time for flag to set
}
while ((IFG1 & OFIFG)); // OSCFault flag still set?
P4SEL |= 0x03; // P4.1,0 = USART1 TXD/RXD
ME2 |= UTXE1 + URXE1; // Enable USART1 TXD/RXD
U1CTL |= CHAR; // 8-bit character
U1TCTL |= SSEL0; // UCLK = ACLK
U1BR0 = 0x03; // 32k/9600 - 3.41
U1BR1 = 0x00; //
U1MCTL = 0x4A; // Modulation
U1CTL &= ~SWRST; // Initialize USART state machine
IE2 |= URXIE1; // Enable USART1 RX interrupt
_BIS_SR(LPM3_bits + GIE); // Enter LPM3 w/ interrupt
}
#pragma vector=USART1RX_VECTOR
__interrupt void USART1_rx (void)
{
while (!(IFG2 & UTXIFG1)); // USART1 TX buffer ready?
TXBUF1 = RXBUF1; // RXBUF1 to TXBUF1
}
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -