📄 fet440_tb_02.c
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//******************************************************************************
// MSP-FET430P440 Demo - Timer_B, Toggle P5.1, CCR0 Up Mode ISR, DCO SMCLK
//
// Description: Toggle P5.1 using software and TB_0 ISR. Timer_B is
// configured for up mode, thus the timer overflows when TBR counts to
// CCR0. In this example, CCR0 is loaded with 20000.
// ACLK = n/a, MCLK = SMCLK = TBCLK = default DCO
//
// MSP430F449
// ---------------
// /|\| XIN|-
// | | |
// --|RST XOUT|-
// | |
// | P5.1|-->LED
//
// M. Buccini
// Texas Instruments Inc.
// Feb 2005
// Built with IAR Embedded Workbench Version: 3.21A
//******************************************************************************
#include <msp430x44x.h>
void main(void)
{
WDTCTL = WDTPW + WDTHOLD; // Stop WDT
P5DIR |= 0x02; // Set P5.1 to output direction
TBCCTL0 = CCIE; // TBCCR0 interrupt enabled
TBCCR0 = 20000;
TBCTL = TBSSEL_2 + MC_1; // SMCLK, up mode
_BIS_SR(LPM0_bits + GIE); // Enter LPM0 w/ interrupt
}
// Timer B0 interrupt service routine
#pragma vector=TIMERB0_VECTOR
__interrupt void Timer_B (void)
{
P5OUT ^= 0x02; // Toggle P5.1 using exclusive-OR
}
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