mscan0drv.h

freescale最新的16位单片机

/******************************************************************************
Copyright (c) Motorola 2000

File Name           :  $RCSfile: msCAN0drv.h,v $               
        
Engineer            :  $Author: r52458 $

Location            :  EKB

Date Created     	:  25/05/98

Current Revision 	:  $Revision: 1.1 $

Notes            	:  Defines for msCAN module 0.

*******************************************************************************
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product herein to improve reliability, function or design. Motorola does
not assume any liability arising out ot the application or use of any
product, circuit, or software described herein; neither does it convey any
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Motorola and the Motorola logo* are registered trademarks of Motorola Ltd.
******************************************************************************/

        
#ifndef MSCAN0DRV_H
#define MSCAN0DRV_H           /* This header file */

#include "msCANstd.h"
#include "msCANdrv.h"

/******************************************************************************
Number of Message Buffers for msCAN module 0
******************************************************************************/
#define NO_OF_MB_CAN0  16         

/******************************************************************************
Define whether Time Stamp is required for msCAN module 0 messages
******************************************************************************/
#define TIMESTAMP_CAN0 TRUE

/******************************************************************************
Define msCAN module 0 clock source: XTAL or CLK
******************************************************************************/
#define CLKSRC_CAN0 XTAL

/******************************************************************************
Define clock prescaler for msCAN module 0: permitted values 1 to 64
msCAN module 0 clock = CLKSRC_CAN0 / PRESCALER_CAN0
******************************************************************************/
#define PRESCALER_CAN0 2

/******************************************************************************
Define msCAN module 0 bit timing

Permitted values: PROP_SEG_CAN0:   1 to 8 time quanta
                  PHASE_SEG1_CAN0: 1 to 8 time quanta
                                  PHASE_SEG2_CAN0: 2, or PHASE_SEG1_CAN0 if greater
Bit time = (1 + PROP_SEG_CAN0 + PHASE_SEG1_CAN0 + PHASE_SEG2_CAN0) * time quanta
******************************************************************************/
#define PROP_SEG_CAN0   7
#define PHASE_SEG1_CAN0 4
#define PHASE_SEG2_CAN0 4

/******************************************************************************
Define msCAN module 0 re-synchronisation jump width
Permitted values: 1 to smaller of 4 and PHASE_SEG1_CAN0 time quanta
******************************************************************************/
#define RJW_CAN0        4

/******************************************************************************
Define msCAN module 0 listen mode
Permitted values: TRUE:  msCAN in listen mode
                  FALSE: msCAN not in listen mode
******************************************************************************/
#define LISTEN_CAN0 FALSE

 /******************************************************************************
Define msCAN module 0 enable
Permitted values: TRUE:  msCAN in enabled                  
                  FALSE: msCAN not enabled
******************************************************************************/
#define CANENABLE_CAN0 TRUE

/******************************************************************************
Define msCAN module 0 samples per bit
Permitted values: TRUE:  3 samples per bit (PHASE_SEG1_CAN0 >= 2)
                  FALSE: 1 sample  per bit
******************************************************************************/
#define SAMPLEX3_CAN0 TRUE

/******************************************************************************
Define whether msCAN12 module 0 is not clocked when MCU is in WAIT mode
Note: only applies to msCAN12
******************************************************************************/
#define CSWAI_CAN0 FALSE

/******************************************************************************
Define whether activity on the CAN bus will wake-up msCAN module 0 when in SLEEP mode
******************************************************************************/
#define WU_ENABLE_CAN0 TRUE
/******************************************************************************
Define whether wake-up filter is applied to msCAN module 0 when in SLEEP mode
******************************************************************************/
#define WU_FILTER_CAN0 TRUE

/******************************************************************************
Define msCAN Message Object Acceptance Filter
*******************************************************************************
msCAN12 has 8 Identifier Code registers and 8 Identifier Mask registers
These may be configured as:

two  32-bit filters (ID_CODE0_CAN0 to ID_CODE3_CAN0 plus 
                     ID_MASK0_CAN0 to ID_MASK3_CAN0, and
                                         ID_CODE4_CAN0 to ID_CODE7_CAN0 plus 
                                         ID_MASK0_CAN0 to ID_MASK3_CAN0) or

four 16-bit filters (ID_CODE0_CAN0 to ID_CODE1_CAN0 plus 
                     ID_MASK0_CAN0 to ID_MASK1_CAN0, and
                                         ID_CODE2_CAN0 to ID_CODE3_CAN0 plus 
                                         ID_MASK2_CAN0 to ID_MASK3_CAN0, and
                                         ID_CODE4_CAN0 to ID_CODE5_CAN0 plus 
                                         ID_MASK4_CAN0 to ID_MASK5_CAN0, and
                                         ID_CODE6_CAN0 to ID_CODE7_CAN0 plus 
                                         ID_MASK6_CAN0 to ID_MASK7_CAN0) or

eight 8-bit filters (ID_CODE0_CAN0 plus ID_MASK0_CAN0, and
                                         ID_CODE1_CAN0 plus ID_MASK1_CAN0, and
                                         ID_CODE2_CAN0 plus ID_MASK2_CAN0, and
                                         ID_CODE3_CAN0 plus ID_MASK3_CAN0, and
                                         ID_CODE4_CAN0 plus ID_MASK4_CAN0, and
                                         ID_CODE5_CAN0 plus ID_MASK5_CAN0, and
                                         ID_CODE6_CAN0 plus ID_MASK6_CAN0, and
                                         ID_CODE7_CAN0 plus ID_MASK7_CAN0)


All bits of the Arbitration Field of received Message Objects which are not 
masked are tested by each filter on a bit by bit basis, eg the first bit of the
Arbitration Field (ID28 for extended format or ID10 for standard format) is 
tested for a match with bit 7 of ID_CODE0_CAN0 if not masked by bit 7 of  
ID_MASK0_CAN0.  Note that the RTR, IDE and if applicable, SRR bits are also
tested.  If a 16-bit filter is to accept a standard format Message Object, the
3 least significant bits of the filter must be masked. Only Message Objects 
which pass the Acceptance Filter are moved into the msCAN foreground receive 
buffer (from where they are retrieved by this driver), all others are checked 
for errors and then discarded.

*******************************************************************************
Define Message Object Acceptance Filter size for msCAN module 0
Permitted values: AF32BIT (32 bit)
                  AF16BIT (16 bit)
                                  AF8BIT  (8 bit)
******************************************************************************/
#define ACC_FILTER_CAN0 AF32BIT

/******************************************************************************
Define Message Object Acceptance Code for msCAN module 0
These values are written into CANIDAR0 to CANIDAR7
******************************************************************************/
#define ID_CODE0_CAN0 0xFF
#define ID_CODE1_CAN0 0xFF
#define ID_CODE2_CAN0 0xFF
#define ID_CODE3_CAN0 0xFF
#define ID_CODE4_CAN0 0xFF
#define ID_CODE5_CAN0 0xFF
#define ID_CODE6_CAN0 0xFF
#define ID_CODE7_CAN0 0xFF

/******************************************************************************
Define Message Object Acceptance Filter Mask for msCAN module 0
These values are written into CIDMR0 to CIDMR7  
Bit set = mask (ignore) corresponding bit of ID_CODEn_CAN0
******************************************************************************/
#define ID_MASK0_CAN0 0xFF
#define ID_MASK1_CAN0 0xFF
#define ID_MASK2_CAN0 0xFF
#define ID_MASK3_CAN0 0xFF
#define ID_MASK4_CAN0 0xFF
#define ID_MASK5_CAN0 0xFF
#define ID_MASK6_CAN0 0xFF
#define ID_MASK7_CAN0 0xFF

/******************************************************************************
Control register defines : do not change!
******************************************************************************/
#define CANCTL0_CAN0 ((CSWAI_CAN0 << 5)|(TIMESTAMP_CAN0 << 3)|(WU_ENABLE_CAN0 << 2))
#define CANCTL1_CAN0 ((CANENABLE_CAN0 << 7)|(WU_FILTER_CAN0 << 2)|(LISTEN_CAN0 << 4)|(CLKSRC_CAN0 << 6))
#define CANBTR0_CAN0 (((RJW_CAN0 - 1) << 6)|(PRESCALER_CAN0 - 1))
#define CANBTR1_CAN0 ((SAMPLEX3_CAN0 << 7)|((PHASE_SEG2_CAN0 - 1) << 4)|(PROP_SEG_CAN0 + PHASE_SEG1_CAN0 - 1))

/*****************************************************************************/
#endif        /* end msCAN0drv.h */