regs.h

freescale最新的16位单片机

#define LIN_XGIF_ICh3A              0x0400		/* 0x3A interrupt channel flag*/
#define LIN_XGIF_ICh39              0x0200		/* 0x39 interrupt channel flag*/
#define LIN_XGIF_ICh38              0x0100		/* 0x38 interrupt channel flag*/
#define LIN_XGIF_ICh37              0x0080		/* 0x37 interrupt channel flag*/
#define LIN_XGIF_ICh36              0x0040		/* 0x36 interrupt channel flag*/
#define LIN_XGIF_ICh35              0x0020		/* 0x35 interrupt channel flag*/
#define LIN_XGIF_ICh34              0x0010		/* 0x34 interrupt channel flag*/
#define LIN_XGIF_ICh33              0x0008		/* 0x33 interrupt channel flag*/
#define LIN_XGIF_ICh32              0x0004		/* 0x32 interrupt channel flag*/
#define LIN_XGIF_ICh31              0x0002		/* 0x31 interrupt channel flag*/
#define LIN_XGIF_ICh30              0x0001		/* 0x30 interrupt channel flag*/
#define LIN_XGIF_ICh2F              0x8000		/* 0x2F interrupt channel flag*/
#define LIN_XGIF_ICh2E              0x4000		/* 0x2E interrupt channel flag*/
#define LIN_XGIF_ICh2D              0x2000		/* 0x2D interrupt channel flag*/
#define LIN_XGIF_ICh2C              0x1000		/* 0x2C interrupt channel flag*/
#define LIN_XGIF_ICh2B              0x0800		/* 0x2B interrupt channel flag*/
#define LIN_XGIF_ICh2A              0x0400		/* 0x2A interrupt channel flag*/
#define LIN_XGIF_ICh29              0x0200		/* 0x29 interrupt channel flag*/
#define LIN_XGIF_ICh28              0x0100		/* 0x28 interrupt channel flag*/
#define LIN_XGIF_ICh27              0x0080		/* 0x27 interrupt channel flag*/
#define LIN_XGIF_ICh26              0x0040		/* 0x26 interrupt channel flag*/
#define LIN_XGIF_ICh25              0x0020		/* 0x25 interrupt channel flag*/
#define LIN_XGIF_ICh24              0x0010		/* 0x24 interrupt channel flag*/
#define LIN_XGIF_ICh23              0x0008		/* 0x23 interrupt channel flag*/
#define LIN_XGIF_ICh22              0x0004		/* 0x22 interrupt channel flag*/
#define LIN_XGIF_ICh21              0x0002		/* 0x21 interrupt channel flag*/
#define LIN_XGIF_ICh20              0x0001		/* 0x20 interrupt channel flag*/
#define LIN_XGIF_ICh1F              0x8000		/* 0x1F interrupt channel flag*/
#define LIN_XGIF_ICh1E              0x4000		/* 0x1E interrupt channel flag*/
#define LIN_XGIF_ICh1D              0x2000		/* 0x1D interrupt channel flag*/
#define LIN_XGIF_ICh1C              0x1000		/* 0x1C interrupt channel flag*/
#define LIN_XGIF_ICh1B              0x0800		/* 0x1B interrupt channel flag*/
#define LIN_XGIF_ICh1A              0x0400		/* 0x1A interrupt channel flag*/
#define LIN_XGIF_ICh19              0x0200		/* 0x19 interrupt channel flag*/
#define LIN_XGIF_ICh18              0x0100		/* 0x18 interrupt channel flag*/
#define LIN_XGIF_ICh17              0x0080		/* 0x17 interrupt channel flag*/
#define LIN_XGIF_ICh16              0x0040		/* 0x16 interrupt channel flag*/
#define LIN_XGIF_ICh15              0x0020		/* 0x15 interrupt channel flag*/
#define LIN_XGIF_ICh14              0x0010		/* 0x14 interrupt channel flag*/
#define LIN_XGIF_ICh13              0x0008		/* 0x13 interrupt channel flag*/
#define LIN_XGIF_ICh12              0x0004		/* 0x12 interrupt channel flag*/
#define LIN_XGIF_ICh11              0x0002		/* 0x11 interrupt channel flag*/
#define LIN_XGIF_ICh10              0x0001		/* 0x10 interrupt channel flag*/
#define LIN_XGIF_ICh0F              0x8000		/* 0x0F interrupt channel flag*/
#define LIN_XGIF_ICh0E              0x4000		/* 0x0E interrupt channel flag*/
#define LIN_XGIF_ICh0D              0x2000		/* 0x0D interrupt channel flag*/
#define LIN_XGIF_ICh0C              0x1000		/* 0x0C interrupt channel flag*/
#define LIN_XGIF_ICh0B              0x0800		/* 0x0B interrupt channel flag*/
#define LIN_XGIF_ICh0A              0x0400		/* 0x0A interrupt channel flag*/
#define LIN_XGIF_ICh09              0x0200		/* 0x09 interrupt channel flag*/


/**********************  Bits for Register XGSWT *************************/
#define LIN_XGSWT_CH7M              0x8000      /* Software Trigger Mask Bit 7 */
#define LIN_XGSWT_CH6M			    0x4000		/* Software Trigger Mask Bit 6 */
#define LIN_XGSWT_CH5M			    0x2000		/* Software Trigger Mask Bit 5 */
#define LIN_XGSWT_CH4M			    0x1000		/* Software Trigger Mask Bit 4 */
#define LIN_XGSWT_CH3M				0x0800		/* Software Trigger Mask Bit 3 */
#define LIN_XGSWT_CH2M			    0x0400		/* Software Trigger Mask Bit 2 */
#define LIN_XGSWT_CH1M				0x0200		/* Software Trigger Mask Bit 1 */
#define LIN_XGSWT_CH0M				0x0100		/* Software Trigger Mask Bit 0 */

#define LIN_XGSWT_ClearFlag	        0x0000	    /* Clear Software Trigger Bit depents 
                                                   on the Software Trigger Mask Bit*/

#define LIN_XGSWT_CH7SetFlag        0x0080	    /* Software Trigger Bit 7 */
#define LIN_XGSWT_CH6SetFlag        0x0040	    /* Software Trigger Bit 6 */
#define LIN_XGSWT_CH5SetFlag        0x0020	    /* Software Trigger Bit 5 */
#define LIN_XGSWT_CH4SetFlag        0x0010	    /* Software Trigger Bit 4 */
#define LIN_XGSWT_CH3SetFlag        0x0008	    /* Software Trigger Bit 3 */
#define LIN_XGSWT_CH2SetFlag        0x0004	    /* Software Trigger Bit 2 */
#define LIN_XGSWT_CH1SetFlag        0x0002	    /* Software Trigger Bit 1 */
#define LIN_XGSWT_CH0SetFlag        0x0001	    /* Software Trigger Bit 0 */

/**********************  Bits for Register XGSEM *************************/

#define LIN_XGSEM_ClearSEM7	        0x8000		/* Mask to release the semaphore 7 */
#define LIN_XGSEM_ClearSEM6	        0x4000		/* Mask to release the semaphore 6 */
#define LIN_XGSEM_ClearSEM5	        0x2000		/* Mask to release the semaphore 5 */
#define LIN_XGSEM_ClearSEM4	        0x1000		/* Mask to release the semaphore 4 */
#define LIN_XGSEM_ClearSEM3	        0x0800		/* Mask to release the semaphore 3 */
#define LIN_XGSEM_ClearSEM2	        0x0400		/* Mask to release the semaphore 2 */
#define LIN_XGSEM_ClearSEM1	        0x0200		/* Mask to release the semaphore 1 */
#define LIN_XGSEM_ClearSEM0	        0x0100		/* Mask to release the semaphore 0 */

#define LIN_XGSEM_SetSEM7           0x8080		/* Mask to get the semaphore 7 */
#define LIN_XGSEM_SetSEM6           0x4040		/* Mask to get the semaphore 6 */
#define LIN_XGSEM_SetSEM5           0x2020		/* Mask to get the semaphore 5 */
#define LIN_XGSEM_SetSEM4           0x1010		/* Mask to get the semaphore 4 */
#define LIN_XGSEM_SetSEM3           0x0808		/* Mask to get the semaphore 3 */
#define LIN_XGSEM_SetSEM2           0x0404		/* Mask to get the semaphore 2 */
#define LIN_XGSEM_SetSEM1           0x0202		/* Mask to get the semaphore 1 */
#define LIN_XGSEM_SetSEM0           0x0101		/* Mask to get the semaphore 0 */

#define LIN_XGSEM_SEM7              0x0080		/* semaphore bit 7 */
#define LIN_XGSEM_SEM6              0x0040		/* semaphore bit 6 */
#define LIN_XGSEM_SEM5              0x0020		/* semaphore bit 5 */
#define LIN_XGSEM_SEM4              0x0010		/* semaphore bit 4 */
#define LIN_XGSEM_SEM3              0x0008		/* semaphore bit 3 */
#define LIN_XGSEM_SEM2              0x0004		/* semaphore bit 2 */
#define LIN_XGSEM_SEM1              0x0002		/* semaphore bit 1 */
#define LIN_XGSEM_SEM0              0x0001		/* semaphore bit 0 */
			    
/**********************  Bits for Register INT_CFADDR *************************/
#define	LIN_INT_CFADDR_IntChan_0        			0x00		
#define	LIN_INT_CFADDR_IntChan_1        			0x10		
#define	LIN_INT_CFADDR_IntChan_2        			0x20		
#define	LIN_INT_CFADDR_IntChan_3        			0x30		
#define	LIN_INT_CFADDR_IntChan_4        			0x40		
#define	LIN_INT_CFADDR_IntChan_5        			0x50		
#define	LIN_INT_CFADDR_IntChan_6        			0x60		
#define	LIN_INT_CFADDR_IntChan_7        			0x70	 
#define	LIN_INT_CFADDR_IntChan_8                    0x80
#define	LIN_INT_CFADDR_IntChan_9                    0x90
#define	LIN_INT_CFADDR_IntChan_A                    0xA0
#define	LIN_INT_CFADDR_IntChan_B                    0xB0
#define	LIN_INT_CFADDR_IntChan_C                    0xC0
#define	LIN_INT_CFADDR_IntChan_D        			0xD0		
#define	LIN_INT_CFADDR_IntChan_E                    0xE0
#define	LIN_INT_CFADDR_IntChan_F                    0xF0

#define LIN_INT_CFADDR_UseXGate                     0x80
/**********************  Bits for Register CRGFLG *************************/
#define CRGFLG_RTIF                 0x80		/* RTI flag                             */
#define CRGFLG_PORF                 0x40		/* Power on Reset flag                  */
#define CRGFLG_LVRF                 0x20		/* Low Voltage Reset Flag               */
#define CRGFLG_LOCKIF               0x10		/* PLL Lock Interrupt Flag              */
#define CRGFLG_LOCK                 0x08		/* Lock Status Bit                      */
#define CRGFLG_TRACK                0x04		/* Track Status Bit                     */
#define CRGFLG_SCMIF                0x02		/* Self Clock Mode Interrupt Flag       */
#define CRGFLG_SCM                  0x01		/* Self Clock mode Status Bit           */


/**********************  Bits for Register CRGINT *************************/
#define CRGINT_RTIE                 0x80		/* RTI Enable Bit                       */
#define CRGINT_ILAF                 0x40		/* illegal Address Reset Flag           */
#define CRGINT_LOCKIE               0x10		/* PLL Lock Interrupt Enable Bit        */
#define CRGINT_SCMIE                0x02		/* Self Clock Mode Interrupt Enable Bit */


/**********************  Bits for Register CRGSEL *************************/
#define CRGSEL_PLLSEL               0x80		/* PLL Select Bit                       */
#define CRGSEL_PSTP                 0x40		/* Pseudo Stop Bit                      */
#define CRGSEL_PLLWAI               0x08		/* PLL stops in Wait Mode Bit           */
#define CRGSEL_RTIWAI               0x02		/* RTI stops in Wait Mode Bit           */
#define CRGSEL_COPWAI               0x01		/* COP stops in Wait Mode Bit           */


/**********************  Bits for Register RTICTL *************************/
#define RTICTL_RTDEC                0x80		/* Decimal or Binary divider Select bit */

#endif /* !define (REGS_H) */