📄 regs.h
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#define INT_CFDATA6 (*(volatile char *)0x012E) /* Interrupt Request Configuration Data Registers 6 */
#define INT_CFDATA7 (*(volatile char *)0x012F) /* Interrupt Request Configuration Data Registers 7 */
#define XGMCTL (*(volatile int *)0x0380) /* XGATE Module Control Register */
#define XGVBR (*(volatile int *)0x0386) /* XGATE Vector Base Address Register - low word */
#define XGIF7 (*(volatile int *)0x0388) /* XGATE Channel 7x interrupt Flag Vector */
#define XGIF6 (*(volatile int *)0x038A) /* XGATE Channel 6x interrupt Flag Vector */
#define XGIF5 (*(volatile int *)0x038C) /* XGATE Channel 5x interrupt Flag Vector */
#define XGIF4 (*(volatile int *)0x038E) /* XGATE Channel 4x interrupt Flag Vector */
#define XGIF3 (*(volatile int *)0x0390) /* XGATE Channel 3x interrupt Flag Vector */
#define XGIF2 (*(volatile int *)0x0392) /* XGATE Channel 2x interrupt Flag Vector */
#define XGIF1 (*(volatile int *)0x0394) /* XGATE Channel 1x interrupt Flag Vector */
#define XGIF0 (*(volatile int *)0x0396) /* XGATE Channel 0x interrupt Flag Vector */
#define XGSWT (*(volatile int *)0x0398) /* XGATE Software Trigger Register */
#define XGSEM (*(volatile int *)0x039A) /* XGATE Semaphore Register */
/******************************* LIN Register *******************************/
#define LIN_PORTA PORTA /* Port A Data Register */
#define LIN_PORTB PORTB /* Port B Data Register */
#define LIN_DDRA DDRA /* Port A Data Direction */
#define LIN_DDRB DDRB /* Port B Data Direction */
#define LIN_PUCR PUCR /* Pull-up Control Register */
#define LIN_DBG_PORT LIN_PORTA
#define LIN_DDR LIN_DDRA
#define LIN_SCIBDH SCIBDH /* SCI 1 baud rate high - are accessible if the AMAP bit in the SCISR2 register is set to zero */
#define LIN_SCIBDL SCIBDL /* SCI 1 baud rate low - are accessible if the AMAP bit in the SCISR2 register is set to zero */
#define LIN_SCICR1 SCICR1 /* SCI 1 control register 1 - are accessible if the AMAP bit in the SCISR2 register is set to zero */
#define LIN_SCICR2 SCICR2 /* SCI 1 control register 2 */
#define LIN_SCISR1 SCISR1 /* SCI 1 status register 1 */
#define LIN_SCISR2 SCISR2 /* SCI 1 status register 2 */
#define LIN_SCIDRH SCIDRH /* SCI 1 data register high */
#define LIN_SCIDRL SCIDRL /* SCI 1 data register low */
#define LIN_SCIASR1 SCIASR1 /* SCI Alternative Status Register 1 - are accessible if the AMAP bit in the SCISR2 register is set to one */
#define LIN_SCIACR1 SCIACR1 /* SCI Alternative Control Register 1 - are accessible if the AMAP bit in the SCISR2 register is set to one */
#define LIN_SCIACR2 SCIACR2 /* SCI Alternative Control Register 2 - are accessible if the AMAP bit in the SCISR2 register is set to one */
#define LIN_PITCFLMT PITCFLMT /* PIT Control and Force Load Micro Timer Register */
#define LIN_PITFLT PITFLT /* PIT Force Load Timer Register */
#define LIN_PITCE PITCE /* PIT Channel Enable Register */
#define LIN_PITMUX PITMUX /* PIT Multiplex Register */
#define LIN_PITINTE PITINTE /* PIT Interrupt Enable Register */
#define LIN_PITTF PITTF /* PIT Time-out Flag Register */
#define LIN_PITMTLD0 PITMTLD0 /* PIT Micro Timer Load Register 0 */
#define LIN_PITMTLD1 PITMTLD1 /* PIT Micro Timer Load Register 1 */
#if defined (CHANNEL_0)
#define LIN_PITLD PITLD0 /* PIT Load Register 0 */
#define LIN_PITCNT PITCNT0 /* PIT Count Register 0 */
#elif defined (CHANNEL_1)
#define LIN_PITLD PITLD1 /* PIT Load Register 1 */
#define LIN_PITCNT PITCNT1 /* PIT Count Register 1 */
#elif defined (CHANNEL_2)
#define LIN_PITLD PITLD2 /* PIT Load Register 2 */
#define LIN_PITCNT PITCNT2 /* PIT Count Register 2 */
#elif defined (CHANNEL_3)
#define LIN_PITLD PITLD3 /* PIT Load Register 3 */
#define LIN_PITCNT PITCNT3 /* PIT Count Register 3 */
#endif /*defined (CHANNEL_0)*/
#define LIN_DIRECT DIRECT /* Direct Register */
#define LIN_IVBR IVBR /* Interrupt Vector Base Register */
#define LIN_INT_XGPRIO INT_XGPRIO /* XGATE Interrupt Priority Configuration Register */
#define LIN_INT_CFADDR INT_CFADDR /* Interrupt Request Configuration Address Register */
#define LIN_INT_CFDATA0 INT_CFDATA0 /* Interrupt Request Configuration Data Registers 0 */
#define LIN_INT_CFDATA1 INT_CFDATA1 /* Interrupt Request Configuration Data Registers 1 */
#define LIN_INT_CFDATA2 INT_CFDATA2 /* Interrupt Request Configuration Data Registers 2 */
#define LIN_INT_CFDATA3 INT_CFDATA3 /* Interrupt Request Configuration Data Registers 3 */
#define LIN_INT_CFDATA4 INT_CFDATA4 /* Interrupt Request Configuration Data Registers 4 */
#define LIN_INT_CFDATA5 INT_CFDATA5 /* Interrupt Request Configuration Data Registers 5 */
#define LIN_INT_CFDATA6 INT_CFDATA6 /* Interrupt Request Configuration Data Registers 6 */
#define LIN_INT_CFDATA7 INT_CFDATA7 /* Interrupt Request Configuration Data Registers 7 */
#define LIN_XGMCTL XGMCTL /* XGATE Module Control Register */
#define LIN_XGVBR XGVBR /* XGATE Vector Base Address Register - low word */
#define LIN_XGIF7 XGIF7 /* XGATE Channel 7x interrupt Flag Vector */
#define LIN_XGIF6 XGIF6 /* XGATE Channel 6x interrupt Flag Vector */
#define LIN_XGIF5 XGIF5 /* XGATE Channel 5x interrupt Flag Vector */
#define LIN_XGIF4 XGIF4 /* XGATE Channel 4x interrupt Flag Vector */
#define LIN_XGIF3 XGIF3 /* XGATE Channel 3x interrupt Flag Vector */
#define LIN_XGIF2 XGIF2 /* XGATE Channel 2x interrupt Flag Vector */
#define LIN_XGIF1 XGIF1 /* XGATE Channel 1x interrupt Flag Vector */
#define LIN_XGIF0 XGIF0 /* XGATE Channel 0x interrupt Flag Vector */
#define LIN_XGSWT XGSWT /* XGATE Software Trigger Register */
#define LIN_XGSEM XGSEM /* XGATE Semaphore Register */
/******************************* SCI bits ***********************************/
#define LIN_PUCR_PUPDE 0x08 /* Pull-up Port D Enable */
#define LIN_PUCR_PUPCE 0x04 /* Pull-up Port C Enable */
#define LIN_PUCR_PUPBE 0x02 /* Pull-up Port B Enable */
#define LIN_PUCR_PUPAE 0x01 /* Pull-up Port A Enable */
/********************** Bits for Register SCI1BDH *************************/
#define LIN_SCI1BDH_IREN 0x80 /* Infrared Enable Bit */
#define LIN_SCI1BDH_TNP1 0x40 /* Transmitter Narrow Pulse Bits */
#define LIN_SCI1BDH_TNP0 0x20 /* Transmitter Narrow Pulse Bits */
/********************** Bits for Register SCI1C1 *************************/
#define LIN_SCI1C1_LOOPS 0x80 /* Loop Select Bit */
#define LIN_SCI1C1_SCISWAI 0x40 /* SCI Stop in Wait Mode Bit */
#define LIN_SCI1C1_RSRC 0x20 /* Receiver Source Bit */
#define LIN_SCI1C1_M 0x10 /* Data Format Mode Bit */
#define LIN_SCI1C1_WAKE 0x08 /* Wakeup Condition Bit */
#define LIN_SCI1C1_ILT 0x04 /* Idle Line Type Bit */
#define LIN_SCI1C1_PE 0x02 /* Parity Enable Bit */
#define LIN_SCI1C1_PT 0x01 /* Parity Type Bit */
/********************** Bits for Register SCIASR1 *************************/
#define LIN_SCIASR1_RXEDGIF 0x80 /* Receive Input Active Edge Interrupt Flag */
#define LIN_SCIASR1_BERRV 0x04 /* Bit Error Value */
#define LIN_SCIASR1_BERRIF 0x02 /* Bit Error Interrupt Flag */
#define LIN_SCIASR1_BKDIF 0x01 /* Break Detect Interrupt Flag */
/********************** Bits for Register SCIACR1 *************************/
#define LIN_SCIACR1_RXEDGIE 0x80 /* Receive Input Active Edge Interrupt Enable */
#define LIN_SCIACR1_BERRIE 0x02 /* Bit Error Interrupt Enable */
#define LIN_SCIACR1_BKDIE 0x01 /* Break Detect Interrupt Enable */
/********************** Bits for Register SCIACR2 *************************/
#define LIN_SCIACR2_BERRM1 0x04 /* Bit Error Mode */
#define LIN_SCIACR2_BERRM0 0x02 /* Bit Error Mode */
#define LIN_SCIACR2_BKDFE 0x01 /* Break Detect Feature Enable */
/********************** Bits for Register SCICR2 *************************/
#define LIN_SCICR2_TIE 0x80 /* Transmitter Interrupt Enable Bit */
#define LIN_SCICR2_TCIE 0x40 /* Transmission Complete Interrupt Enable Bit */
#define LIN_SCICR2_RIE 0x20 /* Receiver Full Interrupt Enable Bit */
#define LIN_SCICR2_ILIE 0x10 /* Idle Line Interrupt Enable Bit */
#define LIN_SCICR2_TE 0x08 /* Transmitter Enable Bit */
#define LIN_SCICR2_RE 0x04 /* Receiver Enable Bit */
#define LIN_SCICR2_RWU 0x02 /* Receiver Wakeup Bit */
#define LIN_SCICR2_SBK 0x01 /* Send Break Bit */
/********************** Bits for Register SCISR1 *************************/
#define LIN_SCISR1_TDRE 0x80 /* Transmit Data Register Empty Flag */
#define LIN_SCISR1_TC 0x40 /* Transmit Complete Flag */
#define LIN_SCISR1_RDRF 0x20 /* Receive Data Register Full Flag */
#define LIN_SCISR1_IDLE 0x10 /* Idle Line Flag */
#define LIN_SCISR1_OR 0x08 /* Overrun Flag */
#define LIN_SCISR1_NF 0x04 /* Noise Flag */
#define LIN_SCISR1_FE 0x02 /* Framing Error Flag */
#define LIN_SCISR1_PF 0x01 /* Parity Error Flag */
/********************** Bits for Register SCISR2 *************************/
#define LIN_SCISR2_AMAP 0x80 /* Alternative Map */
#define LIN_SCISR2_TXPOL 0x10 /* Transmit Polarity */
#define LIN_SCISR2_RXPOL 0x08 /* Receive Polarity */
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