📄 regs.h
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#ifndef REGS_H
#define REGS_H
/******************************************************************************
*
* Copyright (C) 2005 Freescale Semiconductor, Inc.
* All Rights Reserved
*
* Filename: regs.h
*
* Functions: Register definition file for S12XDP512
*
* Description:
*
* Notes:
*
******************************************************************************/
/******************************* I/O Register *******************************/
#define PORTA (*(volatile char *)0x0000) /* Port A Data Register */
#define PORTB (*(volatile char *)0x0001) /* Port B Data Register */
#define DDRA (*(volatile char *)0x0002) /* Port A Data Direction */
#define DDRB (*(volatile char *)0x0003) /* Port B Data Direction */
#define PORTC (*(volatile char *)0x0004) /* Port A Data Register */
#define PORTD (*(volatile char *)0x0005) /* Port B Data Register */
#define DDRC (*(volatile char *)0x0006) /* Port A Data Direction */
#define DDRD (*(volatile char *)0x0007) /* Port B Data Direction */
#define PUCR (*(volatile char *)0x000C) /* Pull-up Control Register */
#define PTP (*(volatile char *)0x0258) /* Port P Data Register */
#define PTIP (*(volatile char *)0x0259) /* Port P Input Register */
#define DDRP (*(volatile char *)0x025A) /* Port P Data Direction Register */
#define RDRP (*(volatile char *)0x025B) /* Port P Reduced Drive Register */
#define PERP (*(volatile char *)0x025C) /* Port P Pull Device Enable Register */
#define PPSP (*(volatile char *)0x025D) /* Port P Polarity Select Register */
#define PIEP (*(volatile char *)0x025E) /* Port P Interrupt Enable Register */
#define PIFP (*(volatile char *)0x025F) /* Port P Interrupt Flag Register */
/******************************* SCI Register *******************************/
#if defined(SCI0)
#define SCIBDH (*(volatile char *)0x00C8) /* SCI 0 baud rate high - are accessible if the AMAP bit in the SCISR2 register is set to zero */
#define SCIBDL (*(volatile char *)0x00C9) /* SCI 0 baud rate low - are accessible if the AMAP bit in the SCISR2 register is set to zero */
#define SCICR1 (*(volatile char *)0x00CA) /* SCI 0 control register 1 - are accessible if the AMAP bit in the SCISR2 register is set to zero */
#define SCICR2 (*(volatile char *)0x00CB) /* SCI 0 control register 2 */
#define SCISR1 (*(volatile char *)0x00CC) /* SCI 0 status register 1 */
#define SCISR2 (*(volatile char *)0x00CD) /* SCI 0 status register 2 */
#define SCIDRH (*(volatile char *)0x00CE) /* SCI 0 data register high */
#define SCIDRL (*(volatile char *)0x00CF) /* SCI 0 data register low */
#define SCIASR1 (*(volatile char *)0x00C8) /* SCI 0 Alternative Status Register 1 - are accessible if the AMAP bit in the SCISR2 register is set to one */
#define SCIACR1 (*(volatile char *)0x00C9) /* SCI 0 Alternative Control Register 1 - are accessible if the AMAP bit in the SCISR2 register is set to one */
#define SCIACR2 (*(volatile char *)0x00CA) /* SCI 0 Alternative Control Register 2 - are accessible if the AMAP bit in the SCISR2 register is set to one */
#elif defined(SCI1)
#define SCIBDH (*(volatile char *)0x00D0) /* SCI 1 baud rate high - are accessible if the AMAP bit in the SCISR2 register is set to zero */
#define SCIBDL (*(volatile char *)0x00D1) /* SCI 1 baud rate low - are accessible if the AMAP bit in the SCISR2 register is set to zero */
#define SCICR1 (*(volatile char *)0x00D2) /* SCI 1 control register 1 - are accessible if the AMAP bit in the SCISR2 register is set to zero */
#define SCICR2 (*(volatile char *)0x00D3) /* SCI 1 control register 2 */
#define SCISR1 (*(volatile char *)0x00D4) /* SCI 1 status register 1 */
#define SCISR2 (*(volatile char *)0x00D5) /* SCI 1 status register 2 */
#define SCIDRH (*(volatile char *)0x00D6) /* SCI 1 data register high */
#define SCIDRL (*(volatile char *)0x00D7) /* SCI 1 data register low */
#define SCIASR1 (*(volatile char *)0x00D0) /* SCI 1 Alternative Status Register 1 - are accessible if the AMAP bit in the SCISR2 register is set to one */
#define SCIACR1 (*(volatile char *)0x00D1) /* SCI 1 Alternative Control Register 1 - are accessible if the AMAP bit in the SCISR2 register is set to one */
#define SCIACR2 (*(volatile char *)0x00D2) /* SCI 1 Alternative Control Register 2 - are accessible if the AMAP bit in the SCISR2 register is set to one */
#elif defined(SCI2)
#define SCIBDH (*(volatile char *)0x00B8) /* SCI 2 baud rate high - are accessible if the AMAP bit in the SCISR2 register is set to zero */
#define SCIBDL (*(volatile char *)0x00B9) /* SCI 2 baud rate low - are accessible if the AMAP bit in the SCISR2 register is set to zero */
#define SCICR1 (*(volatile char *)0x00BA) /* SCI 2 control register 1 - are accessible if the AMAP bit in the SCISR2 register is set to zero */
#define SCICR2 (*(volatile char *)0x00BB) /* SCI 2 control register 2 */
#define SCISR1 (*(volatile char *)0x00BC) /* SCI 2 status register 1 */
#define SCISR2 (*(volatile char *)0x00BD) /* SCI 2 status register 2 */
#define SCIDRH (*(volatile char *)0x00BE) /* SCI 2 data register high */
#define SCIDRL (*(volatile char *)0x00BF) /* SCI 2 data register low */
#define SCIASR1 (*(volatile char *)0x00B8) /* SCI 2 Alternative Status Register 1 - are accessible if the AMAP bit in the SCISR2 register is set to one */
#define SCIACR1 (*(volatile char *)0x00B9) /* SCI 2 Alternative Control Register 1 - are accessible if the AMAP bit in the SCISR2 register is set to one */
#define SCIACR2 (*(volatile char *)0x00BA) /* SCI 2 Alternative Control Register 2 - are accessible if the AMAP bit in the SCISR2 register is set to one */
#elif defined(SCI3)
#define SCIBDH (*(volatile char *)0x00C0) /* SCI 3 baud rate high - are accessible if the AMAP bit in the SCISR2 register is set to zero */
#define SCIBDL (*(volatile char *)0x00C1) /* SCI 3 baud rate low - are accessible if the AMAP bit in the SCISR2 register is set to zero */
#define SCICR1 (*(volatile char *)0x00C2) /* SCI 3 control register 1 - are accessible if the AMAP bit in the SCISR2 register is set to zero */
#define SCICR2 (*(volatile char *)0x00C3) /* SCI 3 control register 2 */
#define SCISR1 (*(volatile char *)0x00C4) /* SCI 3 status register 1 */
#define SCISR2 (*(volatile char *)0x00C5) /* SCI 3 status register 2 */
#define SCIDRH (*(volatile char *)0x00C6) /* SCI 3 data register high */
#define SCIDRL (*(volatile char *)0x00C7) /* SCI 3 data register low */
#define SCIASR1 (*(volatile char *)0x00C0) /* SCI 3 Alternative Status Register 1 - are accessible if the AMAP bit in the SCISR2 register is set to one */
#define SCIACR1 (*(volatile char *)0x00C1) /* SCI 3 Alternative Control Register 1 - are accessible if the AMAP bit in the SCISR2 register is set to one */
#define SCIACR2 (*(volatile char *)0x00C2) /* SCI 3 Alternative Control Register 2 - are accessible if the AMAP bit in the SCISR2 register is set to one */
#elif defined(SCI4)
#define SCIBDH (*(volatile char *)0x0130) /* SCI 4 baud rate high - are accessible if the AMAP bit in the SCISR2 register is set to zero */
#define SCIBDL (*(volatile char *)0x0131) /* SCI 4 baud rate low - are accessible if the AMAP bit in the SCISR2 register is set to zero */
#define SCICR1 (*(volatile char *)0x0132) /* SCI 4 control register 1 - are accessible if the AMAP bit in the SCISR2 register is set to zero */
#define SCICR2 (*(volatile char *)0x0133) /* SCI 4 control register 2 */
#define SCISR1 (*(volatile char *)0x0134) /* SCI 4 status register 1 */
#define SCISR2 (*(volatile char *)0x0135) /* SCI 4 status register 2 */
#define SCIDRH (*(volatile char *)0x0136) /* SCI 4 data register high */
#define SCIDRL (*(volatile char *)0x0137) /* SCI 4 data register low */
#define SCIASR1 (*(volatile char *)0x0130) /* SCI 4 Alternative Status Register 1 - are accessible if the AMAP bit in the SCISR2 register is set to one */
#define SCIACR1 (*(volatile char *)0x0131) /* SCI 4 Alternative Control Register 1 - are accessible if the AMAP bit in the SCISR2 register is set to one */
#define SCIACR2 (*(volatile char *)0x0132) /* SCI 4 Alternative Control Register 2 - are accessible if the AMAP bit in the SCISR2 register is set to one */
#elif defined(SCI5)
#define SCIBDH (*(volatile char *)0x0138) /* SCI 5 baud rate high - are accessible if the AMAP bit in the SCISR2 register is set to zero */
#define SCIBDL (*(volatile char *)0x0139) /* SCI 5 baud rate low - are accessible if the AMAP bit in the SCISR2 register is set to zero */
#define SCICR1 (*(volatile char *)0x013A) /* SCI 5 control register 1 - are accessible if the AMAP bit in the SCISR2 register is set to zero */
#define SCICR2 (*(volatile char *)0x013B) /* SCI 5 control register 2 */
#define SCISR1 (*(volatile char *)0x013C) /* SCI 5 status register 1 */
#define SCISR2 (*(volatile char *)0x013D) /* SCI 5 status register 2 */
#define SCIDRH (*(volatile char *)0x013E) /* SCI 5 data register high */
#define SCIDRL (*(volatile char *)0x013F) /* SCI 5 data register low */
#define SCIASR1 (*(volatile char *)0x0138) /* SCI 5 Alternative Status Register 1 - are accessible if the AMAP bit in the SCISR2 register is set to one */
#define SCIACR1 (*(volatile char *)0x0139) /* SCI 5 Alternative Control Register 1 - are accessible if the AMAP bit in the SCISR2 register is set to one */
#define SCIACR2 (*(volatile char *)0x013A) /* SCI 5 Alternative Control Register 2 - are accessible if the AMAP bit in the SCISR2 register is set to one */
#endif /* defined(SCI0) */
/******************************* Timer Register *****************************/
#define PITCFLMT (*(volatile char *)0x0340) /* PIT Control and Force Load Micro Timer Register */
#define PITFLT (*(volatile char *)0x0341) /* PIT Force Load Timer Register */
#define PITCE (*(volatile char *)0x0342) /* PIT Channel Enable Register */
#define PITMUX (*(volatile char *)0x0343) /* PIT Multiplex Register */
#define PITINTE (*(volatile char *)0x0344) /* PIT Interrupt Enable Register */
#define PITTF (*(volatile char *)0x0345) /* PIT Time-out Flag Register */
#define PITMTLD0 (*(volatile char *)0x0346) /* PIT Micro Timer Load Register 0 */
#define PITMTLD1 (*(volatile char *)0x0347) /* PIT Micro Timer Load Register 1 */
#define PITLD0 (*(volatile int *)0x0348) /* PIT Load Register 0 */
#define PITCNT0 (*(volatile int *)0x034A) /* PIT Count Register 0 */
#define PITLD1 (*(volatile int *)0x034C) /* PIT Load Register 1 */
#define PITCNT1 (*(volatile int *)0x034E) /* PIT Count Register 1 */
#define PITLD2 (*(volatile int *)0x0350) /* PIT Load Register 2 */
#define PITCNT2 (*(volatile int *)0x0352) /* PIT Count Register 2 */
#define PITLD3 (*(volatile int *)0x0354) /* PIT Load Register 3 */
#define PITCNT3 (*(volatile int *)0x0356) /* PIT Count Register 3 */
/******************************* Special Register *****************************/
#define DIRECT (*(volatile char *)0x0011) /* Direct Register */
#define CRGFLG (*(volatile char *)0x0037) /* CRG Flags Register */
#define CRGINT (*(volatile char *)0x0038) /* CRG Interrupt Enable Register */
#define CLKSEL (*(volatile char *)0x0039) /* CRG Clock Select Register */
#define RTICTL (*(volatile char *)0x003B) /* RTI Control Register */
#define IVBR (*(volatile char *)0x0121) /* Interrupt Vector Base Register */
#define INT_XGPRIO (*(volatile char *)0x0126) /* XGATE Interrupt Priority Configuration Register */
#define INT_CFADDR (*(volatile char *)0x0127) /* Interrupt Request Configuration Address Register */
#define INT_CFDATA0 (*(volatile char *)0x0128) /* Interrupt Request Configuration Data Registers 0 */
#define INT_CFDATA1 (*(volatile char *)0x0129) /* Interrupt Request Configuration Data Registers 1 */
#define INT_CFDATA2 (*(volatile char *)0x012A) /* Interrupt Request Configuration Data Registers 2 */
#define INT_CFDATA3 (*(volatile char *)0x012B) /* Interrupt Request Configuration Data Registers 3 */
#define INT_CFDATA4 (*(volatile char *)0x012C) /* Interrupt Request Configuration Data Registers 4 */
#define INT_CFDATA5 (*(volatile char *)0x012D) /* Interrupt Request Configuration Data Registers 5 */
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