📄 regs.h
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#define LIN_SCISR2_BRK13 0x04 /* Break Transmit character length */
#define LIN_SCISR2_TXDIR 0x02 /* Transmitter pin data direction in Single-Wire mode */
#define LIN_SCISR2_RAF 0x01 /* Receiver Active Flag */
/****************************** Timer bits **********************************/
/********************** Bits for Register PITCFLMT *************************/
#define LIN_PITCFLMT_PITE 0x80 /* PIT Module Enable Bit */
#define LIN_PITCFLMT_PITSWAI 0x40 /* PIT Stop in Wait Mode Bit */
#define LIN_PITCFLMT_PITFRZ 0x20 /* PIT Counter Freeze while in Freeze Mode Bit */
#define LIN_PITCFLMT_PFLMT1 0x02 /* PIT Force Load Bits for Micro Timer 1 */
#define LIN_PITCFLMT_PFLMT0 0x01 /* PIT Force Load Bits for Micro Timer 0 */
/********************** Bits for Register PITFLT *************************/
#if defined (CHANNEL_3)
#define LIN_PITFLT_PFLT 0x08 /* PIT Force Load Bits for Timer 3 */
#elif defined (CHANNEL_2)
#define LIN_PITFLT_PFLT 0x04 /* PIT Force Load Bits for Timer 2 */
#elif defined (CHANNEL_1)
#define LIN_PITFLT_PFLT 0x02 /* PIT Force Load Bits for Timer 1 */
#elif defined (CHANNEL_0)
#define LIN_PITFLT_PFLT 0x01 /* PIT Force Load Bits for Timer 0 */
#endif /* defined (CHANNEL_3) */
/********************** Bits for Register PITCE *************************/
#if defined (CHANNEL_3)
#define LIN_PITCE_PCE 0x08 /* PIT Enable Bits for Timer Channel 3 */
#elif defined (CHANNEL_2)
#define LIN_PITCE_PCE 0x04 /* PIT Enable Bits for Timer Channel 2 */
#elif defined (CHANNEL_1)
#define LIN_PITCE_PCE 0x02 /* PIT Enable Bits for Timer Channel 1 */
#elif defined (CHANNEL_0)
#define LIN_PITCE_PCE 0x01 /* PIT Enable Bits for Timer Channel 0 */
#endif /* defined (CHANNEL_3) */
/********************** Bits for Register PITMUX *************************/
#if defined (CHANNEL_3)
#define LIN_PITMUX_PMUX 0x08 /* PIT Multiplex Bits for Timer Channel 3 */
#elif defined (CHANNEL_2)
#define LIN_PITMUX_PMUX 0x04 /* PIT Multiplex Bits for Timer Channel 2 */
#elif defined (CHANNEL_1)
#define LIN_PITMUX_PMUX 0x02 /* PIT Multiplex Bits for Timer Channel 1 */
#elif defined (CHANNEL_0)
#define LIN_PITMUX_PMUX 0x01 /* PIT Multiplex Bits for Timer Channel 0 */
#endif /* defined (CHANNEL_3) */
/********************** Bits for Register PITINTE *************************/
#if defined (CHANNEL_3)
#define LIN_PITINTE_PINTE 0x08 /* PIT Time-out Interrupt Enable Bits for Timer Channel 3 */
#elif defined (CHANNEL_2)
#define LIN_PITINTE_PINTE 0x04 /* PIT Time-out Interrupt Enable Bits for Timer Channel 2 */
#elif defined (CHANNEL_1)
#define LIN_PITINTE_PINTE 0x02 /* PIT Time-out Interrupt Enable Bits for Timer Channel 1 */
#elif defined (CHANNEL_0)
#define LIN_PITINTE_PINTE 0x01 /* PIT Time-out Interrupt Enable Bits for Timer Channel 0 */
#endif /* defined (CHANNEL_3) */
/********************** Bits for Register PITTF *************************/
#if defined (CHANNEL_3)
#define LIN_PITTF_PTF 0x08 /* PIT Time-out Flag Bits for Timer Channel 3 */
#elif defined (CHANNEL_2)
#define LIN_PITTF_PTF 0x04 /* PIT Time-out Flag Bits for Timer Channel 2 */
#elif defined (CHANNEL_1)
#define LIN_PITTF_PTF 0x02 /* PIT Time-out Flag Bits for Timer Channel 1 */
#elif defined (CHANNEL_0)
#define LIN_PITTF_PTF 0x01 /* PIT Time-out Flag Bits for Timer Channel 0 */
#endif /* defined (CHANNEL_3) */
/****************************** Special bits **********************************/
/********************** Bits for Register XGMCTL *************************/
#define LIN_XGMCTL_XGEM 0x8000 /* XGE Mask */
#define LIN_XGMCTL_XGFRZM 0x4000 /* XGFRZ Mask */
#define LIN_XGMCTL_XGDBGM 0x2000 /* XGDBG Mask */
#define LIN_XGMCTL_XGSSM 0x1000 /* XGSS Mask */
#define LIN_XGMCTL_XGFACTM 0x0800 /* XGFACT Mask */
#define LIN_XGMCTL_XGSWEIFM 0x0200 /* XGSWEIF Mask */
#define LIN_XGMCTL_XGIEM 0x0100 /* XGIE Mask */
#define LIN_XGMCTL_XGE 0x0080 /* XGATE Module Enable */
#define LIN_XGMCTL_XGFRZ 0x0040 /* Halt XGATE in Freeze Mode */
#define LIN_XGMCTL_XGDBG 0x0020 /* XGATE Debug Mode */
#define LIN_XGMCTL_XGSS 0x0010 /* XGATE Single Step */
#define LIN_XGMCTL_XGFACT 0x0008 /* Fake XGATE Activity */
#define LIN_XGMCTL_XGSWEIF 0x0002 /* XGATE Software Error Interrupt Flag */
#define LIN_XGMCTL_XGIE 0x0001 /* XGATE Interrupt Enable */
/********************** Bits for Register XGIF *************************/
#define LIN_XGIF_ICh78 0x0100 /* 0x78 interrupt channel flag*/
#define LIN_XGIF_ICh77 0x0080 /* 0x77 interrupt channel flag*/
#define LIN_XGIF_ICh76 0x0040 /* 0x76 interrupt channel flag*/
#define LIN_XGIF_ICh75 0x0020 /* 0x75 interrupt channel flag*/
#define LIN_XGIF_ICh74 0x0010 /* 0x74 interrupt channel flag*/
#define LIN_XGIF_ICh73 0x0008 /* 0x73 interrupt channel flag*/
#define LIN_XGIF_ICh72 0x0004 /* 0x72 interrupt channel flag*/
#define LIN_XGIF_ICh71 0x0002 /* 0x71 interrupt channel flag*/
#define LIN_XGIF_ICh70 0x0001 /* 0x70 interrupt channel flag*/
#define LIN_XGIF_ICh6F 0x8000 /* 0x6F interrupt channel flag*/
#define LIN_XGIF_ICh6E 0x4000 /* 0x6E interrupt channel flag*/
#define LIN_XGIF_ICh6D 0x2000 /* 0x6D interrupt channel flag*/
#define LIN_XGIF_ICh6C 0x1000 /* 0x6C interrupt channel flag*/
#define LIN_XGIF_ICh6B 0x0800 /* 0x6B interrupt channel flag*/
#define LIN_XGIF_ICh6A 0x0400 /* 0x6A interrupt channel flag*/
#define LIN_XGIF_ICh69 0x0200 /* 0x69 interrupt channel flag*/
#define LIN_XGIF_ICh68 0x0100 /* 0x68 interrupt channel flag*/
#define LIN_XGIF_ICh67 0x0080 /* 0x67 interrupt channel flag*/
#define LIN_XGIF_ICh66 0x0040 /* 0x66 interrupt channel flag*/
#define LIN_XGIF_ICh65 0x0020 /* 0x65 interrupt channel flag*/
#define LIN_XGIF_ICh64 0x0010 /* 0x64 interrupt channel flag*/
#define LIN_XGIF_ICh63 0x0008 /* 0x63 interrupt channel flag*/
#define LIN_XGIF_ICh62 0x0004 /* 0x62 interrupt channel flag*/
#define LIN_XGIF_ICh61 0x0002 /* 0x61 interrupt channel flag*/
#define LIN_XGIF_ICh60 0x0001 /* 0x60 interrupt channel flag*/
#define LIN_XGIF_ICh5F 0x8000 /* 0x5F interrupt channel flag*/
#define LIN_XGIF_ICh5E 0x4000 /* 0x5E interrupt channel flag*/
#define LIN_XGIF_ICh5D 0x2000 /* 0x5D interrupt channel flag*/
#define LIN_XGIF_ICh5C 0x1000 /* 0x5C interrupt channel flag*/
#define LIN_XGIF_ICh5B 0x0800 /* 0x5B interrupt channel flag*/
#define LIN_XGIF_ICh5A 0x0400 /* 0x5A interrupt channel flag*/
#define LIN_XGIF_ICh59 0x0200 /* 0x59 interrupt channel flag*/
#define LIN_XGIF_ICh58 0x0100 /* 0x58 interrupt channel flag*/
#define LIN_XGIF_ICh57 0x0080 /* 0x57 interrupt channel flag*/
#define LIN_XGIF_ICh56 0x0040 /* 0x56 interrupt channel flag*/
#define LIN_XGIF_ICh55 0x0020 /* 0x55 interrupt channel flag*/
#define LIN_XGIF_ICh54 0x0010 /* 0x54 interrupt channel flag*/
#define LIN_XGIF_ICh53 0x0008 /* 0x53 interrupt channel flag*/
#define LIN_XGIF_ICh52 0x0004 /* 0x52 interrupt channel flag*/
#define LIN_XGIF_ICh51 0x0002 /* 0x51 interrupt channel flag*/
#define LIN_XGIF_ICh50 0x0001 /* 0x50 interrupt channel flag*/
#define LIN_XGIF_ICh4F 0x8000 /* 0x4F interrupt channel flag*/
#define LIN_XGIF_ICh4E 0x4000 /* 0x4E interrupt channel flag*/
#define LIN_XGIF_ICh4D 0x2000 /* 0x4D interrupt channel flag*/
#define LIN_XGIF_ICh4C 0x1000 /* 0x4C interrupt channel flag*/
#define LIN_XGIF_ICh4B 0x0800 /* 0x4B interrupt channel flag*/
#define LIN_XGIF_ICh4A 0x0400 /* 0x4A interrupt channel flag*/
#define LIN_XGIF_ICh49 0x0200 /* 0x49 interrupt channel flag*/
#define LIN_XGIF_ICh48 0x0100 /* 0x48 interrupt channel flag*/
#define LIN_XGIF_ICh47 0x0080 /* 0x47 interrupt channel flag*/
#define LIN_XGIF_ICh46 0x0040 /* 0x46 interrupt channel flag*/
#define LIN_XGIF_ICh45 0x0020 /* 0x45 interrupt channel flag*/
#define LIN_XGIF_ICh44 0x0010 /* 0x44 interrupt channel flag*/
#define LIN_XGIF_ICh43 0x0008 /* 0x43 interrupt channel flag*/
#define LIN_XGIF_ICh42 0x0004 /* 0x42 interrupt channel flag*/
#define LIN_XGIF_ICh41 0x0002 /* 0x41 interrupt channel flag*/
#define LIN_XGIF_ICh40 0x0001 /* 0x40 interrupt channel flag*/
#define LIN_XGIF_ICh3F 0x8000 /* 0x3F interrupt channel flag*/
#define LIN_XGIF_ICh3E 0x4000 /* 0x3E interrupt channel flag*/
#define LIN_XGIF_ICh3D 0x2000 /* 0x3D interrupt channel flag*/
#define LIN_XGIF_ICh3C 0x1000 /* 0x3C interrupt channel flag*/
#define LIN_XGIF_ICh3B 0x0800 /* 0x3B interrupt channel flag*/
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