📄 distancetranformf_l.sa.bak
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* ------------------------------------------------------------------------- *
* Copyright (c) 2002 Texas Instruments, Incorporated. *
* All Rights Reserved. *
* ========================================================================= *
.text
.global _DistanceTransformf_L
_DistanceTransformf_L: .cproc A_in1, A_in2, A_in3, A_out, A_w,weight1,weight2,weight3
.no_mdep
* ========================================================================= *
* Array access *
* ========================================================================= *
;.reg B_in1, B_in2,B_in3,A_out
;.reg A_wD4, A_wD8
;.reg B_wD4, B_wD8
* ========================================================================= *
* Coeffcients *
* ========================================================================= *
.reg A_add1, B_add2, A_add3
.reg mask1,mask2,mask3,mask4
* ========================================================================= *
* Input pixels *
* ========================================================================= *
.reg A_in1_h:A_in1_l ; |x|x|x|x|x|x|x|x| | |
.reg B_in2_h:B_in2_l ; |x|x|x|x|x|x|x|x| | |
.reg A_in3_h:A_in3_l ; |x|x|x|x|x|x|x|x| | |
* ========================================================================= *
* Temporary values *
* ========================================================================= *
.reg A_contr1:A_contr1l,A_contr2:A_contr2l
.reg B_contr3:B_contr3l,B_contr4:B_contr4l
.reg B_contr5:B_contr5l,B_contr6:B_contr6l
.reg B_contr7:B_contr7l,A_contr8:A_contr8l
.reg A_contr9:A_contr9l,A_contr12:A_contr12l
.reg B_contr34:B_contr34l,B_contr56:B_contr56l
.reg A_contr79:A_contr79l,A_contr1279:A_contr1279l
.reg B_contr3456:B_contr3456l
.reg A_result,A_result1:A_result1l
.reg A_temp1,A_temp2,A_temp3,A_temp4,B_temp1,B_temp2
.reg A_temp0,B_temp3,B_temp4,A_seed
* ========================================================================= *
* Control *
* ========================================================================= *
.reg A_cnt ; Loop counter
.reg B_final
* ========================================================================= *
* ========================================================================= *
* Setup *
* ========================================================================= *
MVK 0X000000FF, mask1
MVKH 0X000000FF, mask1
MVK 0X0000FF00, mask2
MVKH 0X0000FF00, mask2
MVK 0X00FF0000, mask3
MVKH 0X00FF0000, mask3
MVK 0XFF000000, mask4
MVKH 0XFF000000, mask4
MVK 0X0000FFFF, mask5
MVKH 0X0000FFFF, mask5
MVK 0XFFFF0000, mask6
MVKH 0XFFFF0000, mask6
SHL weight3, 16, A_temp1
OR weight3, A_temp1, A_add3 ; add coefficient weight3
SHL weight2, 16, B_temp1
OR weight2, B_temp1, B_add2 ; add coefficient weight2
SHL weight1, 16, A_temp2
OR weight2, A_temp1, A_add1 ; add coefficient weight1
LDW *A_in3, A_temp1
AND A_temp1, mask2, A_temp1
SHRU A_temp1, 8, A_seed ;element 18
MV A_w, A_cnt
SHRU A_cnt, 2, A_cnt
MV A_cnt, B_final
SUB A_cnt, 2, A_cnt ; loop control
* ========================================================================= *
* Loop *
* ========================================================================= *
loop: .trip 4
LDNDW.D1T1 *A_in3, A_in3_h:A_in3_l ; A load, line 3
LDNDW.D2T2 *A_in2, B_in2_h:B_in2_l ; A load, line 2
LDNDW.D1T1 *A_in1, A_in1_h:A_in1_l ; A load, line 1
; Horizontal filter mask:
ZERO A_contr1
ZERO A_contr2
ZERO B_contr3
ZERO B_contr4
ZERO B_contr5
ZERO B_contr6
ZERO B_contr7
ZERO A_contr8
ZERO A_contr9
AND mask2, A_in1_l, A_temp1
SHRU A_temp1, 8, A_temp1
OR A_temp1, A_contr1, A_contr1l
AND A_in1_l, mask3, A_temp2
OR A_temp2, A_contr1, A_contr1l
AND A_in1_l, mask4, A_temp3
SHRU A_temp3, 24, A_temp3
OR A_temp3, A_contr1, A_contr1
OR A_temp3, A_contr2l, A_contr2l
AND A_in1_h, mask1, A_temp1
SHL A_temp1, 16, A_temp1
OR A_temp1, A_contr1, A_contr1
OR A_temp1, A_contr2l, A_contr2l
AND A_in1_h, mask2, A_temp2
SHRU A_temp2, 8, A_temp2
OR A_temp2, A_contr2, A_contr2
AND A_in1_h, mask3, A_temp3
OR A_temp3, A_contr2, A_contr2 ;the first line finished
ADD2 A_contr1, A_add3, A_contr1
ADD2 A_contr1l, A_add3, A_contr1l
ADD2 A_contr2, A_add3, A_contr2
ADD2 A_contr2l, A_add3, A_contr2l ;add finished
MINU2 A_contr1, A_contr2, A_contr12
MINU2 A_contr1l, A_contr2l, A_contr12l;compare
AND B_in2_l, mask1, B_temp1
OR B_temp1, B_contr3l, B_contr3l
AND B_in2_l, mask2, B_temp2
SHRU B_temp2, 8, B_temp2
OR B_temp2, B_contr4l, B_contr4l
SHL B_temp2, 16, B_temp2
OR B_temp2, B_contr3l, B_contr3l
AND B_in2_l, mask3, B_temp3
OR B_temp3, B_contr4l, B_contr4l
SHRU B_temp3, 16, B_temp3
OR B_temp3, B_contr3, B_contr3
OR B_temp3, B_contr5l, B_contr5l
AND B_in2_l, mask4, B_temp4
SHRU B_temp4, 8, B_temp4
OR B_temp4, B_contr3, B_contr3
OR B_temp4, B_contr5l, B_contr5l
SHRU B_temp4, 16, B_temp4
OR B_temp4, B_contr4, B_contr4
OR B_temp4, B_contr6l, B_contr6l
AND B_in2_h, mask1, B_temp1
OR B_temp1, B_contr7l, B_contr7l
OR B_temp1, B_contr5, B_contr5
SHL B_temp1, 16, B_temp1
OR B_temp1, B_contr4, B_contr4
OR B_temp1, B_contr6l, B_contr6l
AND B_in2_h, mask2, B_temp2
SHRU B_temp2, 8, B_temp2
OR B_temp2, B_contr6, B_contr6
SHL B_temp2, 16, B_temp2
OR B_temp2, B_contr5, B_contr5
OR B_temp2, B_contr7l, B_contr7l
AND B_in2_h, mask3, B_temp3
OR B_temp3, B_contr6, B_contr6
SHRU B_temp3, 16, B_temp3
OR B_temp3, B_contr7l, B_contr7l
AND B_in2_h, mask4, B_temp4
SHRU B_temp4, 8, B_temp4
OR B_temp4, B_contr7, B_contr7 ;the second line finnished
ADD2 B_contr3, A_add3, B_contr3
ADD2 B_contr3l, A_add3, B_contr3l
ADD2 B_contr4, B_add2, B_contr4
ADD2 B_contr4l, B_add2, B_contr4l
ADD2 B_contr5, A_add1, B_contr5
ADD2 B_contr5l, A_add1, B_contr5l
ADD2 B_contr6, B_add2, B_contr6
ADD2 B_contr6l, B_add2, B_contr6l
ADD2 B_contr7, A_add3, B_contr7
ADD2 B_contr7l, A_add3, B_contr7l; add finished
MINU2 B_contr3, B_contr4, B_contr34
MINU2 B_contr3l, B_contr4l, B_contr34l ;compare
MINU2 B_contr5, B_contr6, B_contr56
MINU2 B_contr5l, B_contr6l, B_contr56l ;compare
OR A_seed, A_contr8l, A_contr8l ;element 18
AND A_in3_l, mask3, A_temp1
SHRU A_temp1, 16, A_temp1
OR A_temp1, A_contr9l, A_contr9l
AND A_in3_l, mask4, A_temp2
SHRU A_temp2, 8, A_temp2
OR A_temp2, A_contr9l, A_contr9l
AND A_in3_h, mask1, A_temp3
OR A_temp3, A_contr9, A_contr9
AND A_in3_h, mask2, A_temp4
SHL A_temp4, 8, A_temp4
OR A_temp4, A_contr9, A_contr9 ; the third line finished
MINU2 B_contr7, A_contr9, A_contr79
MINU2 B_contr7l, A_contr9l, A_contr79l
MINU2 A_contr12, A_contr79, A_contr1279
MINU2 A_contr12l, A_contr79l, A_contr1279l;compare
MINU2 B_contr56, B_contr34, B_contr3456
MINU2 B_contr56l, B_contr34l, B_contr3456l;compare
MINU2 A_contr1279,B_contr3456, A_result1
MINU2 A_contr1279l,B_contr3456l, A_result1l ;compare
ZERO A_result
ADD2 A_contr8l, A_add1, A_temp0
MINU2 A_temp0, A_result1l, A_temp1 ;compare
AND A_temp1, mask1, A_temp1
OR A_temp1, A_result, A_result
SHL A_temp1, 16, A_temp2
ADD A_temp2, A_add1, A_temp2
MINU2 A_temp2, A_result1l, A_temp2
AND A_temp2, mask3, A_temp2
SHRU A_temp2, 8, A_temp2
OR A_temp2, A_result, A_result
SHRU A_temp2, 8, A_temp3
ADD A_temp3, A_add1, A_temp3
MINU2 A_temp3, A_result1, A_temp3
AND A_temp3, mask1, A_temp3
SHL A_temp3, 16, A_temp3
OR A_temp3, A_result, A_result
ADD A_temp3, A_add1, A_temp4
MINU2 A_temp4, A_result1, A_temp4
AND A_temp4, mask3, A_temp4
SHL A_temp4, 8, A_temp4
OR A_temp4, A_result, A_result
AND A_result, mask4, A_seed
SHRU A_seed, 24, A_seed
ADD A_in3, 4, A_in3
ADD A_in2, 4, A_in2
ADD A_in1, 4, A_in1
SUB B_final, 1, B_final
[B_final] STW.D2T1 A_result, *A_out++
BDEC loop, A_cnt
.return
.endproc
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