📄 distancetranformb_l.asm
字号:
.line 77
NOP 1
SHRU .S2X A3,0x10,B24 ; |84| element 18
.line 79
.line 80
SHRU .S1 A8,0x2,A5 ; |87|
.line 81
.line 82
ADD .D1 0xfffffffe,A5,A3 ; |89| loop control
.line 87
LDNDW .D1T1 *A27,A19:A18 ; |96| (P) <0,2> A load, line 3
LDNDW .D1T1 *A4,A21:A20 ; |98| (P) <0,1> A load, line 1
LDNDW .D2T2 *B5,B21:B20 ; |97| (P) <0,0> A load, line 2
MV .D1X B26,A31
NOP 1
ZERO .L2 B9:B8 ; |105| (P) <0,3>
|| MVC .S2 CSR,B11
|| AND .D1X A19,B29,A29 ; |196| (P) <0,9>
ZERO .L2 B7:B6 ; |104| (P) <0,5>
|| AND .D2 -2,B11,B4
|| AND .D1X A18,B29,A8 ; |213| (P) <0,7>
ADD .D1 0xffffffff,A5,A0 ; |266| (P) <0,25>
|| SUB .S1 A4,4,A28 ; |98| (P) <0,1>
|| SUB .D2 B5,4,B28 ; |97| (P) <0,0>
|| ZERO .L2 B17:B16 ; |103| (P) <0,0>
|| MVC .S2 B4,CSR ; interrupts off
|| AND .L1X A21,B29,A4 ; |114| (P) <0,6>
ZERO .D1 A26 ; |231| (P) <0,17>
|| ZERO .L1 A17:A16 ; |106| (P) <0,4>
|| ZERO .L2 B5:B4 ; |107| (P) <0,1>
|| AND .D2 B21,B29,B19 ; |138| (P) <0,6>
|| AND .S2X B20,A1,B0 ; |160| (P) <0,7>
|| AND .S1X B21,A1,A25 ; |133| (P) <0,5>
AND .D1 A20,A1,A23 ; |125| (P) <0,6>
|| AND .D2 B21,B26,B30 ; |145| (P) <0,5>
|| AND .L2 B20,B29,B1 ; |166| (P) <0,6>
|| AND .L1X A20,B27,A20 ; |121| (P) <0,19>
|| SHRU .S2 B0,0x10,B31 ; |162| (P) <0,12>
|| SHRU .S1 A25,0x10,A2 ; |135| (P) <0,6>
ZERO .L1 A5:A4 ; |102| (P) <0,2>
|| AND .D2X A21,B26,B10 ; |118| (P) <0,8>
|| SHRU .S2 B1,0x8,B18 ; |167| (P) <0,11>
|| AND .L2 B21,B27,B21 ; |129| (P) <0,8>
|| SHL .S1 A4,0x8,A24 ; |115| (P) <0,7>
|| OR .D1X B0,A16,A16 ; |161| (P) <0,10>
ZERO .L1 A7:A6 ; |109| (P) <0,3>
|| AND .D2 B20,B27,B0 ; |152| (P) <0,7>
|| SHL .S1X B30,0x10,A21 ; |148| (P) <0,11>
|| SHRU .S2 B21,0x8,B3 ; |130| (P) <0,9>
|| OR .D1 A24,A5,A5 ; |116| (P) <0,13>
|| AND .L2X A19,B26,B21 ; |200| (P) <0,9>
ZERO .L1 A9:A8 ; |108| (P) <0,5>
|| SHRU .S1 A8,0x8,A24 ; |214| (P) <0,8>
|| SHRU .S2 B19,0x8,B19 ; |139| (P) <0,7>
|| OR .D2X A25,B7,B7 ; |134| (P) <0,10>
|| OR .D1X B10,A5,A5 ; |119| (P) <0,17>
|| OR .L2 B3,B17,B17 ; |131| (P) <0,15>
AND .D1 A19,A1,A10 ; |193| (P) <0,7>
|| SHL .S2 B18,0x10,B21 ; |169| (P) <0,14>
|| OR .D2 B19,B7,B7 ; |140| (P) <0,13>
|| OR .L2X A2,B17,B17 ; |136| (P) <0,19>
|| AND .L1 A18,A1,A19 ; |210| (P) <0,9>
|| SHL .S1X B21,0x10,A22 ; |201| (P) <0,16>
AND .D2 B20,B26,B20 ; |172| (P) <0,16>
|| OR .D1 A10,A9,A9 ; |194| (P) <0,12>
|| SHL .S2 B19,0x10,B2 ; |141| (P) <0,8>
|| ADD2 .L2X B7,A30,B7 ; |177| (P) <0,22>
|| OR .L1 A19,A6,A6 ; |211| (P) <0,10>
|| SHRU .S1X B0,0x8,A19 ; |153| (P) <0,12>
OR .D1X B18,A16,A16 ; |168| (P) <0,13>
|| OR .D2 B2,B16,B16 ; |142| (P) <0,10>
|| OR .L1 A21,A17,A17 ; |150| (P) <0,12>
|| OR .S2 B2,B9,B9 ; |143| (P) <0,9>
|| OR .L2X A21,B6,B6 ; |149| (P) <0,13>
|| SHRU .S1 A29,0x8,A21 ; |197| (P) <0,13>
ZERO .L2 B19:B18 ; |101| (P) <0,18>
|| OR .D2 B30,B9,B9 ; |147| (P) <0,10>
|| AND .D1X A18,B27,A18 ; |205| (P) <0,14>
|| OR .L1 A24,A6,A6 ; |215| (P) <0,11> the third line finished
|| SHRU .S1 A19,0x10,A24 ; |156| (P) <0,14>
|| OR .S2X A19,B5,B5 ; |154| (P) <0,23>
ADD2 .D2 B17,B23,B17 ; |175| (P) <0,20>
|| ADD2 .S2 B9,B22,B9 ; |179| (P) <0,11>
|| OR .D1 A21,A9,A9 ; |198| (P) <0,14>
|| ADD2 .S1X A6,B23,A6 ; |220| (P) <0,20>
|| OR .L2X A19,B8,B8 ; |155| (P) <0,14>
|| OR .L1 A24,A17,A17 ; |158| (P) <0,15>
SUB .D1 A27,4,A29 ; |96| (P) <0,2>
|| OR .D2 B21,B4,B4 ; |170| (P) <0,19>
|| MIN2 .L2 B17,B7,B7 ; |186| (P) <0,23>
|| ADD2 .S1X A9,B23,A9 ; |217| (P) <0,15>
|| OR .S2X A24,B6,B6 ; |157| (P) <0,16>
|| ADD2 .L1 A17,A30,A17 ; |181| (P) <0,16>
SUB .D1 A3,1,A11
|| SHRU .S1 A20,0x8,A18 ; |122| (P) <0,21>
|| OR .D2 B20,B4,B4 ; |173| (P) <0,25> the second line finnished
|| OR .L2 B30,B16,B16 ; |146| (P) <0,11>
|| MIN2 .L1X B9,A17,A17 ; |188| (P) <0,18>
|| SHRU .S2X A18,0x18,B9 ; |206| (P) <0,20>
ADD2 .D1 A16,A30,A16 ; |182| (P) <0,16>
|| ADD2 .D2 B16,B23,B16 ; |176| (P) <0,12>
|| OR .S1 A22,A7,A7 ; |202| (P) <0,18>
|| OR .S2 B31,B8,B8 ; |163| (P) <0,15>
|| ADD2 .L2X B6,A30,B6 ; |178| (P) <0,17>
|| MIN2 .L1X A17,B7,A3 ; |226| (P) <0,25>
OR .D1 A18,A4,A4 ; |123| (P) <0,22>
|| SHRU .S1 A23,0x10,A21 ; |126| (P) <0,15>
|| OR .D2 B31,B5,B5 ; |164| (P) <0,24>
|| ADD2 .S2 B8,B22,B8 ; |180| (P) <0,17>
|| MIN2 .L2 B16,B6,B6 ; |187| (P) <0,21> compare
|| OR .L1X B9,A7,A7 ; |207| (P) <0,22>
OR .D1 A22,A8,A8 ; |203| (P) <0,18>
|| OR .S1 A21,A4,A4 ; |127| (P) <0,23> the first line finished
|| ADD2 .D2 B5,B23,B5 ; |183| (P) <0,25>
|| MIN2 .L2X B8,A16,B8 ; |189| (P) <0,24> compare
|| SHL .S2 B24,0x10,B16 ; |111| (P) <0,24> ^
|| ADD2 .L1X A7,B23,A7 ; |219| (P) <0,23>
;*----------------------------------------------------------------------------*
;* SOFTWARE PIPELINE INFORMATION
;*
;* Loop source line : 96
;* Loop closing brace source line : 269
;* Known Minimum Trip Count : 4
;* Known Max Trip Count Factor : 1
;* Loop Carried Dependency Bound(^) : 24
;* Unpartitioned Resource Bound : 24
;* Partitioned Resource Bound(*) : 25
;* Resource Partition:
;* A-side B-side
;* .L units 14 13
;* .S units 13 11
;* .D units 2 2
;* .M units 0 0
;* .X cross paths 25* 19
;* .T address paths 4 3
;* Long read paths 0 0
;* Long write paths 4 5
;* Logical ops (.LS) 0 0 (.L or .S unit)
;* Addition ops (.LSD) 40 48 (.L or .S or .D unit)
;* Bound(.L .S .LS) 14 12
;* Bound(.L .S .D .LS .LSD) 23 25*
;*
;* Searching for software pipeline schedule at ...
;* ii = 25 Register is live too long
;* |108| -> |222|
;* |109| -> |222|
;* |108| -> |221|
;* |109| -> |221|
;* |103| -> |187|
;* |107| -> |191|
;* |104| -> |187|
;* |105| -> |189|
;* |107| -> |190|
;* |103| -> |186|
;* |105| -> |188|
;* ii = 25 Did not find schedule
;* ii = 26 Register is live too long
;* |104| -> |187|
;* |109| -> |222|
;* |108| -> |222|
;* |109| -> |221|
;* |103| -> |187|
;* |106| -> |188|
;* |108| -> |221|
;* ii = 26 Did not find schedule
;* ii = 27 Register is live too long
;* |109| -> |222|
;* |107| -> |191|
;* |109| -> |221|
;* ii = 27 Did not find schedule
;* ii = 28 Register is live too long
;* |101| -> |255|
;* |109| -> |222|
;* |108| -> |222|
;* ii = 28 Register is live too long
;* |104| -> |187|
;* ii = 29 Register is live too long
;* |105| -> |189|
;* ii = 30 Register is live too long
;* |102| -> |191|
;* |102| -> |190|
;* ii = 30 Register is live too long
;* |101| -> |255|
;* ii = 30 Did not find schedule
;* ii = 31 Register is live too long
;* |102| -> |191|
;* |102| -> |190|
;* ii = 31 Schedule found with 2 iterations in parallel
;*
;* Register Usage Table:
;* +-----------------------------------------------------------------+
;* |AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA|BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB|
;* |00000000001111111111222222222233|00000000001111111111222222222233|
;* |01234567890123456789012345678901|01234567890123456789012345678901|
;* |--------------------------------+--------------------------------|
;* 0: |** ******* * * ****| *** ** * ** ** ***** |
;* 1: |** ****** * * ****| ** * ** ** ***** |
;* 2: |** ****** * * ****| * ** ** ** ***** |
;* 3: |** ****** * * ****| ** ** ** ***** |
;* 4: |** **** * * * ****| ** ** ** ***** |
;* 5: |** * * * * * * ****| ** ** ** ***** |
;* 6: |** ** * * * ****| ** **** ** ***** |
;* 7: |** * * * * ****| **** **** ** ***** |
;* 8: |** *** * * * ****| **** **** ** ***** |
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