📄 distancetranform_l.asm
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;******************************************************************************
;* TMS320C6x C/C++ Codegen PC Version 4.32 *
;* Date/Time created: Mon Mar 19 11:00:41 2007 *
;******************************************************************************
;******************************************************************************
;* GLOBAL FILE PARAMETERS *
;* *
;* Architecture : TMS320C64xx *
;* Optimization : Enabled at level 3 *
;* Optimizing for : Speed *
;* Based on options: -o3, no -ms *
;* Endian : Little *
;* Interrupt Thrshld : Disabled *
;* Memory Model : Small *
;* Calls to RTS : Near *
;* Pipelining : Enabled *
;* Speculative Load : Disabled *
;* Memory Aliases : Presume are aliases (pessimistic) *
;* Debug Info : COFF Debug *
;* *
;******************************************************************************
.asg A15, FP
.asg B14, DP
.asg B15, SP
.global $bss
.file "serial_asm"
* ------------------------------------------------------------------------- *
* Copyright (c) 2002 Texas Instruments, Incorporated. *
* All Rights Reserved. *
* ========================================================================= *
.text
.global _DistanceTransform_L
.sect ".text"
.file "DistanceTranform_L.sa"
.sym _DistanceTransform_L,_DistanceTransform_L, 32, 3, 0
.func 8
;******************************************************************************
;* FUNCTION NAME: _DistanceTransform_L *
;* *
;* Regs Modified : A0,A3,A4,A5,A6,A7,A8,A9,B0,B1,B4,B5,B6,B7,B8,B9,A16, *
;* A17,A18,A19,A20,A21,A22,A23,A24,A25,A26,A27,A28, *
;* A29,B16,B17,B18,B19,B20,B21,B22,B23,B24,B25,B26, *
;* B27,B28,B29,B30,B31 *
;* Regs Used : A0,A3,A4,A5,A6,A7,A8,A9,A10,B0,B1,B3,B4,B5,B6,B7,B8, *
;* B9,B10,DP,SP,A16,A17,A18,A19,A20,A21,A22,A23,A24,*
;* A25,A26,A27,A28,A29,B16,B17,B18,B19,B20,B21,B22, *
;* B23,B24,B25,B26,B27,B28,B29,B30,B31 *
;******************************************************************************
;******************************************************************************
;* *
;* Using -g (debug) with optimization (-o3) may disable key optimizations! *
;* *
;******************************************************************************
_DistanceTransform_L:
;** --------------------------------------------------------------------------*
.line 1
.sym A_in1,41, 4, 4, 32
.sym A_in2,20, 4, 4, 32
.sym A_in3,6, 4, 4, 32
.sym A_out,22, 4, 4, 32
.sym A_w,8, 4, 4, 32
.sym weight1,24, 4, 4, 32
.sym weight2,10, 4, 4, 32
.sym weight3,26, 4, 4, 32
; _DistanceTransform_L: .cproc A_in1, A_in2, A_in3, A_out, A_w,weight1,weight2,weight3
; .no_mdep
.sym A_add1,54, 4, 4, 32
.sym B_add2,57, 4, 4, 32
.sym A_add3,59, 4, 4, 32
; .reg A_add1, B_add2, A_add3
.sym mask1,55, 4, 4, 32
.sym mask2,3, 4, 4, 32
.sym mask3,58, 4, 4, 32
.sym mask4,60, 4, 4, 32
; .reg mask1,mask2,mask3,mask4
.sym "A_in1_h:A_in1_l",3, 4, 4, 32
.sym A_in1_l,3, 4, 4, 32
.sym A_in1_h,3, 4, 4, 32
; .reg A_in1_h:A_in1_l ; |x|x|x|x|x|x|x|x| | |
.sym "B_in2_h:B_in2_l",3, 4, 4, 32
.sym B_in2_l,3, 4, 4, 32
.sym B_in2_h,3, 4, 4, 32
; .reg B_in2_h:B_in2_l ; |x|x|x|x|x|x|x|x| | |
.sym "A_in3_h:A_in3_l",3, 4, 4, 32
.sym A_in3_l,3, 4, 4, 32
.sym A_in3_h,3, 4, 4, 32
; .reg A_in3_h:A_in3_l ; |x|x|x|x|x|x|x|x| | |
.sym A_contr1,63, 4, 4, 32
.sym A_contr2,7, 4, 4, 32
.sym B_contr3,25, 4, 4, 32
.sym B_contr4,56, 4, 4, 32
.sym B_contr5,23, 4, 4, 32
.sym B_contr6,53, 4, 4, 32
; .reg A_contr1,A_contr2,B_contr3,B_contr4,B_contr5,B_contr6
.sym B_contr7,40, 4, 4, 32
.sym A_contr8,3, 4, 4, 32
.sym A_contr9,9, 4, 4, 32
.sym A_contr12,3, 4, 4, 32
.sym B_contr34,3, 4, 4, 32
.sym B_contr56,3, 4, 4, 32
; .reg B_contr7,A_contr8,A_contr9,A_contr12,B_contr34,B_contr56
.sym A_contr79,3, 4, 4, 32
.sym A_result,38, 4, 4, 32
.sym A_contr1279,3, 4, 4, 32
.sym B_contr3456,3, 4, 4, 32
.sym A_result1,3, 4, 4, 32
; .reg A_contr79,A_result,A_contr1279,B_contr3456, A_result1
.sym A_temp1,3, 4, 4, 32
.sym A_temp2,3, 4, 4, 32
.sym A_temp3,3, 4, 4, 32
.sym A_temp4,3, 4, 4, 32
.sym B_temp1,3, 4, 4, 32
.sym B_temp2,3, 4, 4, 32
.sym B_temp3,3, 4, 4, 32
.sym B_temp4,3, 4, 4, 32
; .reg A_temp1,A_temp2,A_temp3,A_temp4,B_temp1,B_temp2,B_temp3,B_temp4
.sym A_cnt,4, 4, 4, 32
; .reg A_cnt ; Loop counter
.sym B_final,0, 4, 4, 32
; .reg B_final
; loop: .trip 4
MV .D1 A4,A9 ; |8|
.line 42
MVK .S2 0xff,B18 ; |49|
.line 43
MVKH .S2 0x0,B18 ; |50|
.line 44
MVK .S1 0xff00,A3 ; |51|
.line 45
MVKH .S1 0x0,A3 ; |52|
.line 46
ZERO .D2 B21 ; |53|
.line 47
MVKH .S2 0xff,B21 ; |54|
.line 48
ZERO .D2 B23 ; |55|
.line 49
MVKH .S2 0xff00,B23 ; |56|
.line 51
.line 52
.line 53
.line 54
.line 55
.line 56
.line 57
ZERO .D1 A17 ; |64|
.line 59
SHL .S2 B10,0x18,B7 ; |66|
.line 60
SHL .S2 B10,0x10,B5 ; |67|
.line 61
SHL .S1X B10,0x8,A4 ; |68|
.line 62
OR .D2 B7,B5,B5 ; |69|
.line 63
OR .D1X B10,A4,A4 ; |70|
.line 64
NOP 1
OR .D2X A4,B5,B22 ; |71| add coefficient weight3
.line 66
SHL .S2X A10,0x18,B5 ; |73|
.line 67
SHL .S1 A10,0x10,A4 ; |74|
.line 68
SHL .S1 A10,0x8,A5 ; |75|
.line 69
OR .D2X B5,A4,B5 ; |76|
.line 70
OR .D1 A10,A5,A4 ; |77|
.line 71
NOP 1
OR .D2X A4,B5,B20 ; |78| add coefficient weight2
.line 73
.line 74
.line 75
.line 77
SHL .S1X B8,0x18,A4 ; |84|
.line 78
SHL .S2 B8,0x10,B7 ; |85|
.line 79
SHL .S2 B8,0x8,B5 ; |86|
.line 80
OR .D2X A4,B7,B7 ; |87|
.line 81
OR .D2 B8,B5,B5 ; |88|
.line 82
OR .D2 B5,B7,B17 ; |89| add coefficient weight1
.line 84
ZERO .D2 B24 ; |91|
.line 85
ZERO .D1 A7 ; |92|
.line 86
ZERO .D2 B19 ; |93|
.line 87
ZERO .D2 B9 ; |94|
.line 88
ZERO .D2 B29 ; |95|
.line 89
ZERO .D2 B26 ; |96|
.line 90
ZERO .D1 A20 ; |97|
.line 91
.line 92
ZERO .D1 A18 ; |99|
.line 94
.line 95
SHRU .S1 A8,0x2,A0 ; |102|
.line 96
.line 97
ADD .D1 0xfffffffe,A0,A4 ; |104| loop control
.line 102
MVC .S2 CSR,B1
MV .D2 B4,B8
|| AND .S2 -2,B1,B4
MVC .S2 B4,CSR ; interrupts off
|| LDNDW .D2T2 *B8,B5:B4 ; |112| (P) <0,0> A load, line 2
SUB .S1 A4,2,A16
LDNDW .D1T1 *A9,A5:A4 ; |113| (P) <0,7> A load, line 1
NOP 1
MV .D1 A6,A8
AND .L2 B4,B23,B4 ; |171| (P) <0,10>
|| AND .S2 B4,B18,B25 ; |192| (P) <0,8>
|| AND .D1X B4,A3,A19 ; |187| (P) <0,10>
|| AND .D2 B4,B21,B28 ; |180| (P) <0,10>
AND .S2 B5,B23,B16 ; |147| (P) <0,5>
SHRU .S1X B4,0x8,A25 ; |173| (P) <0,12>
|| AND .D2 B5,B21,B7 ; |150| (P) <0,11>
|| AND .L1 A5,A3,A6 ; |120| (P) <0,12>
;*----------------------------------------------------------------------------*
;* SOFTWARE PIPELINE INFORMATION
;*
;* Loop source line : 111
;* Loop closing brace source line : 252
;* Known Minimum Trip Count : 4
;* Known Max Trip Count Factor : 1
;* Loop Carried Dependency Bound(^) : 12
;* Unpartitioned Resource Bound : 19
;* Partitioned Resource Bound(*) : 22
;* Resource Partition:
;* A-side B-side
;* .L units 7 9
;* .S units 13 15
;* .D units 2 2
;* .M units 0 0
;* .X cross paths 22* 18
;* .T address paths 4 3
;* Long read paths 0 0
;* Long write paths 0 0
;* Logical ops (.LS) 0 0 (.L or .S unit)
;* Addition ops (.LSD) 28 36 (.L or .S or .D unit)
;* Bound(.L .S .LS) 10 12
;* Bound(.L .S .D .LS .LSD) 17 21
;*
;* Searching for software pipeline schedule at ...
;* ii = 22 Schedule found with 3 iterations in parallel
;*
;* Register Usage Table:
;* +-----------------------------------------------------------------+
;* |AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA|BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB|
;* |00000000001111111111222222222233|00000000001111111111222222222233|
;* |01234567890123456789012345678901|01234567890123456789012345678901|
;* |--------------------------------+--------------------------------|
;* 0: |* ******* *********** | ****** ************** *|
;* 1: |* ******* ************* | ****** ************** *|
;* 2: |* ******* ************* | ****** ************** *|
;* 3: |* ******* ************* | ****** ************** |
;* 4: |* ******* ************** | ****** ************* |
;* 5: |* ******* ***** ***** ** | ****** ************* |
;* 6: |* ******* * ****** ** ** | ****** ********** ** |
;* 7: |* ******* * ****** * * | ***** ************ |
;* 8: |* ******* ******** * | ****** ************* |
;* 9: |* ******* ******** | ****** ************* |
;* 10: |* ******* * *** * | ****** ************* |
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