📄 sobel.asm
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;******************************************************************************
;* TMS320C6x C/C++ Codegen PC Version 4.32 *
;* Date/Time created: Wed Feb 14 22:29:07 2007 *
;******************************************************************************
;******************************************************************************
;* GLOBAL FILE PARAMETERS *
;* *
;* Architecture : TMS320C64xx *
;* Optimization : Disabled *
;* Optimizing for : Compile time, Ease of Development *
;* Based on options: no -o, no -ms *
;* Endian : Little *
;* Interrupt Thrshld : Disabled *
;* Memory Model : Small *
;* Calls to RTS : Near *
;* Pipelining : Disabled *
;* Memory Aliases : Presume are aliases (pessimistic) *
;* Debug Info : COFF Debug *
;* *
;******************************************************************************
.asg A15, FP
.asg B14, DP
.asg B15, SP
.global $bss
.file "serial_asm"
* ------------------------------------------------------------------------- *
* Copyright (c) 2002 Texas Instruments, Incorporated. *
* All Rights Reserved. *
* ========================================================================= *
.text
.global _IMG_sobel
.sect ".text"
.file "sobel.sa"
.sym _IMG_sobel,_IMG_sobel, 32, 3, 0
.func 8
;******************************************************************************
;* FUNCTION NAME: _IMG_sobel *
;* *
;* Regs Modified : A0,A3,A4,A5,A6,A7,A8,A9,B0,B1,B4,B5,B6,B7,B8,B9,A16, *
;* A17,A18,A19,A20,A21,A22,A23,A24,A25,A26,A27,A28, *
;* A29,A30,A31,B16,B17,B18,B19,B20,B21,B22,B23,B24, *
;* B25,B26,B27,B28,B29,B30,B31 *
;* Regs Used : A0,A3,A4,A5,A6,A7,A8,A9,B0,B1,B3,B4,B5,B6,B7,B8,B9, *
;* A16,A17,A18,A19,A20,A21,A22,A23,A24,A25,A26,A27, *
;* A28,A29,A30,A31,B16,B17,B18,B19,B20,B21,B22,B23, *
;* B24,B25,B26,B27,B28,B29,B30,B31 *
;******************************************************************************
_IMG_sobel:
;** --------------------------------------------------------------------------*
.line 1
.sym A_in,4, 4, 4, 32
.sym B_out,20, 4, 4, 32
.sym A_w,6, 4, 4, 32
.sym B_h,3, 4, 4, 32
; _IMG_sobel: .cproc A_in, B_out, A_w, B_h
; .no_mdep
.sym B_in,56, 4, 4, 32
.sym A_out,20, 4, 4, 32
; .reg B_in, A_out
.sym A_wD4,38, 4, 4, 32
.sym A_wD8,37, 4, 4, 32
; .reg A_wD4, A_wD8
.sym B_wD4,17, 4, 4, 32
.sym B_wD8,65, 4, 4, 32
; .reg B_wD4, B_wD8
.sym A_mult1,8, 4, 4, 32
.sym A_mult2,5, 4, 4, 32
.sym A_mult1_b,7, 4, 4, 32
.sym A_mult2_b,3, 4, 4, 32
; .reg A_mult1, A_mult2, A_mult1_b, A_mult2_b
.sym B_mult1,55, 4, 4, 32
.sym B_mult2,24, 4, 4, 32
.sym B_mult1_b,25, 4, 4, 32
.sym B_mult2_b,21, 4, 4, 32
; .reg B_mult1, B_mult2, B_mult1_b, B_mult2_b
.sym A_f1,9, 4, 4, 32
.sym A_f2,45, 4, 4, 32
; .reg A_f1, A_f2
.sym B_f1,66, 4, 4, 32
.sym B_f2,57, 4, 4, 32
; .reg B_f1, B_f2
.sym "A_in1_h:A_in1_l",39, 4, 4, 32
.sym A_in1_l,39, 4, 4, 32
.sym A_in1_h,40, 4, 4, 32
; .reg A_in1_h:A_in1_l ; |x|x|x|x|x|x|x|x| | |
.sym "B_tmp2:B_tmp1",53, 4, 4, 32
.sym B_tmp1,53, 4, 4, 32
.sym B_tmp2,54, 4, 4, 32
; .reg B_tmp2:B_tmp1 ; | | |x|x|x|x|x|x|x|x|
.sym "A_in2_l2:A_in2_l",43, 4, 4, 32
.sym A_in2_l,43, 4, 4, 32
.sym A_in2_l2,44, 4, 4, 32
; .reg A_in2_l2:A_in2_l ; |x|x|x|x|x|x|x|x| | |
.sym "B_in2_h2:B_in2_h",61, 4, 4, 32
.sym B_in2_h,61, 4, 4, 32
.sym B_in2_h2,62, 4, 4, 32
; .reg B_in2_h2:B_in2_h ; | | |x|x|x|x|x|x|x|x|
.sym "A_in3_h:A_in3_l",41, 4, 4, 32
.sym A_in3_l,41, 4, 4, 32
.sym A_in3_h,42, 4, 4, 32
; .reg A_in3_h:A_in3_l ; |x|x|x|x|x|x|x|x| | |
.sym "B_tmp4:B_tmp3",22, 4, 4, 32
.sym B_tmp3,22, 4, 4, 32
.sym B_tmp4,23, 4, 4, 32
; .reg B_tmp4:B_tmp3 ; | | |x|x|x|x|x|x|x|x|
.sym A_t1,46, 4, 4, 32
.sym A_t2,6, 4, 4, 32
.sym A_t3,47, 4, 4, 32
.sym A_t4,46, 4, 4, 32
.sym A_t5,6, 4, 4, 32
.sym A_t6,6, 4, 4, 32
.sym A_t7,47, 4, 4, 32
.sym A_t8,46, 4, 4, 32
.sym A_t9,48, 4, 4, 32
.sym A_t10,47, 4, 4, 32
; .reg A_t1, A_t2, A_t3, A_t4, A_t5, A_t6, A_t7, A_t8, A_t9, A_t10
.sym A_t11,46, 4, 4, 32
.sym A_t12,46, 4, 4, 32
; .reg A_t11, A_t12
.sym B_t1,60, 4, 4, 32
.sym B_t2,58, 4, 4, 32
.sym B_t3,63, 4, 4, 32
.sym B_t4,60, 4, 4, 32
.sym B_t5,58, 4, 4, 32
.sym B_t6,58, 4, 4, 32
.sym B_t7,58, 4, 4, 32
.sym B_t8,63, 4, 4, 32
.sym B_t9,64, 4, 4, 32
.sym B_t10,58, 4, 4, 32
; .reg B_t1, B_t2, B_t3, B_t4, B_t5, B_t6, B_t7, B_t8, B_t9, B_t10
.sym B_t11,63, 4, 4, 32
.sym B_t12,58, 4, 4, 32
; .reg B_t11, B_t12
.sym A_H,3, 4, 4, 32
.sym B_H3,3, 4, 4, 32
.sym A_H5,3, 4, 4, 32
.sym B_H7,3, 4, 4, 32
; .reg A_H, B_H3, A_H5, B_H7
.sym A_V2,39, 4, 4, 32
.sym B_V4,23, 4, 4, 32
.sym A_V6,6, 4, 4, 32
.sym B_V8,22, 4, 4, 32
; .reg A_V2, B_V4, A_V6, B_V8
.sym A_b1,54, 4, 4, 32
.sym A_b2,6, 4, 4, 32
.sym A_b3,3, 4, 4, 32
.sym A_b4,3, 4, 4, 32
.sym A_b5,40, 4, 4, 32
.sym A_b6,41, 4, 4, 32
; .reg A_b1, A_b2, A_b3, A_b4, A_b5, A_b6
.sym A_u1,6, 4, 4, 32
.sym A_u2,6, 4, 4, 32
.sym A_u3,54, 4, 4, 32
.sym A_u4,6, 4, 4, 32
.sym A_u5,6, 4, 4, 32
.sym A_u6,39, 4, 4, 32
.sym A_u7,40, 4, 4, 32
.sym A_u8,39, 4, 4, 32
.sym A_u9,39, 4, 4, 32
.sym A_u10,41, 4, 4, 32
; .reg A_u1, A_u2, A_u3, A_u4, A_u5, A_u6, A_u7, A_u8, A_u9, A_u10
.sym A_u11,6, 4, 4, 32
.sym A_u12,6, 4, 4, 32
; .reg A_u11, A_u12
.sym B_b1,3, 4, 4, 32
.sym B_b2,3, 4, 4, 32
.sym B_b3,58, 4, 4, 32
.sym B_b4,22, 4, 4, 32
.sym B_b5,3, 4, 4, 32
.sym B_b6,3, 4, 4, 32
.sym B_b7,53, 4, 4, 32
.sym B_b8,60, 4, 4, 32
; .reg B_b1, B_b2, B_b3, B_b4, B_b5, B_b6, B_b7, B_b8
.sym B_u1,58, 4, 4, 32
.sym B_u2,58, 4, 4, 32
.sym B_u3,39, 4, 4, 32
.sym B_u4,53, 4, 4, 32
.sym B_u5,53, 4, 4, 32
.sym B_u6,22, 4, 4, 32
.sym B_u7,53, 4, 4, 32
.sym B_u8,60, 4, 4, 32
.sym B_u9,60, 4, 4, 32
.sym B_u10,23, 4, 4, 32
; .reg B_u1, B_u2, B_u3, B_u4, B_u5, B_u6, B_u7, B_u8, B_u9, B_u10
.sym B_u11,22, 4, 4, 32
.sym B_u12,22, 4, 4, 32
; .reg B_u11, B_u12
.sym "A_b10_h:A_b10_l",47, 4, 4, 32
.sym A_b10_l,47, 4, 4, 32
.sym A_b10_h,48, 4, 4, 32
.sym "A_b11_h:A_b11_l",49, 4, 4, 32
.sym A_b11_l,49, 4, 4, 32
.sym A_b11_h,50, 4, 4, 32
.sym "A_b12_h:A_b12_l",43, 4, 4, 32
.sym A_b12_l,43, 4, 4, 32
.sym A_b12_h,44, 4, 4, 32
; .reg A_b10_h:A_b10_l, A_b11_h:A_b11_l, A_b12_h:A_b12_l
.sym "B_b14_h:B_b14_l",67, 4, 4, 32
.sym B_b14_l,67, 4, 4, 32
.sym B_b14_h,68, 4, 4, 32
.sym "B_b15_h:B_b15_l",61, 4, 4, 32
.sym B_b15_l,61, 4, 4, 32
.sym B_b15_h,62, 4, 4, 32
.sym "B_b13_h:B_b13_l",63, 4, 4, 32
.sym B_b13_l,63, 4, 4, 32
.sym B_b13_h,64, 4, 4, 32
; .reg B_b14_h:B_b14_l, B_b15_h:B_b15_l, B_b13_h:B_b13_l
.sym A_r9,39, 4, 4, 32
.sym B_r10,40, 4, 4, 32
.sym A_r11,6, 4, 4, 32
.sym B_r12,41, 4, 4, 32
.sym "B_r14:B_r13",39, 4, 4, 32
.sym B_r13,39, 4, 4, 32
.sym B_r14,40, 4, 4, 32
.sym B_r15,3, 4, 4, 32
.sym B_r16,3, 4, 4, 32
; .reg A_r9, B_r10, A_r11, B_r12, B_r14:B_r13, B_r15, B_r16
.sym A_cnt,59, 4, 4, 32
; .reg A_cnt ; Loop counter
.sym B_final,16, 4, 4, 32
; .reg B_final
.line 58
MVKL .S1 0xfeff,A8 ; |65|
.line 59
MVKLH .S1 0xff,A8 ; |66| 0, -1, -2, -1
NOP 1
.line 60
MV .D2X A8,B18 ; |67|
.line 62
MVKL .S1 0x201,A5 ; |69|
.line 63
MVKLH .S1 0x1,A5 ; |70| 0, 1, 2, 1
NOP 1
.line 64
MV .D2X A5,B8 ; |71|
.line 66
MVKL .S1 0xff00,A7 ; |73|
.line 67
MVKLH .S1 0xfffe,A7 ; |74| -1, -2, -1, 0
NOP 1
.line 68
MV .D2X A7,B9 ; |75|
.line 70
MVKL .S1 0x100,A3 ; |77|
.line 71
MVKLH .S1 0x102,A3 ; |78| 1, 2, 1, 0
NOP 1
.line 72
MV .D2X A3,B5 ; |79|
.line 74
MVKL .S1 0x101,A9 ; |81|
.line 75
MVKLH .S1 0x101,A9 ; |82| 1, 1, 1, 1
NOP 1
.line 76
MV .D2X A9,B29 ; |83|
.line 78
MVKL .S1 0x202,A24 ; |85|
.line 79
MVKLH .S1 0x202,A24 ; |86| 2, 2, 2, 2
NOP 1
.line 80
MV .D2X A24,B20 ; |87|
.line 82
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