📄 sobel_asm.asm
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* ------------------------------------------------------------------------- *
* Copyright (c) 2002 Texas Instruments, Incorporated. *
* All Rights Reserved. *
* ========================================================================= *
.text
.global _IMG_sobel
_IMG_sobel:
* ================= SYMBOLIC REGISTER ASSIGNMENTS: SETUP ================== *
.asg B15, B_SP ; Stack pointer, B datapath
.asg A1, A_SP ; Stack pointer, A datapath
.asg B1, B_no_gie ; CSR w/ GIE bit cleared
.asg B3, B_ret ; Return address
.asg B2, B_csr ; CSR's value
* ================= SYMBOLIC REGISTER ASSIGNMENTS: INPUT PARAMETERS ======= *
.asg A4, A_in ; input image pointer
.asg B4, B_out ; output image pointer
.asg A6, A_w ; image width
.asg B6, B_h ; image height
* ================= SYMBOLIC REGISTER ASSIGNMENTS: ARRAY ACCESS =========== *
.asg B8, B_in ; copy of input image pointer
.asg A16, A_wD4 ; image width / 4
.asg A17, A_wD8 ; image width / 8
.asg B9, B_wD4 ; copy of image width / 4
.asg B0, B_wD8 ; copy of image width / 8
.asg A8, A_out ; copy of image output ptr
.asg A26, A_in1_l ; input pixels 0-3, 1st line
.asg A27, A_in1_h ; input pixels 4-7, 1st line
.asg A26, A_in2_l ; input pixels 0-3, 2nd line
.asg A27, A_in2_l2 ; input pixels 4-7, 2nd line
.asg A30, A_in3_l ; input pixels 0-3, 3rd line
.asg A31, A_in3_h ; input pixels 4-7, 3rd line
; input lines with offset 2:
.asg B26, B_tmp1 ; input pixels 0-3, 1st line
.asg B27, B_tmp2 ; input pixels 4-7, 1st line
.asg B26, B_in2_h ; input pixels 0-3, 2nd line
.asg B27, B_in2_h2 ; input pixels 4-7, 2nd line
.asg B30, B_tmp3 ; input pixels 0-3, 3rd line
.asg B31, B_tmp4 ; input pixels 4-7, 3rd line
* ================= SYMBOLIC REGISTER ASSIGNMENTS: COEFFICIENTS =========== *
.asg A20, A_mult1 ; 0, -1, -2, -1
.asg B18, B_mult1 ; 0, -1, -2, -1
.asg A21, A_mult1_b ; -1, -2, -1, 0
.asg B19, B_mult1_b ; -1, -2, -1, 0
.asg A22, A_mult2 ; 0, 1, 2, 1
.asg B20, B_mult2 ; 0, 1, 2, 1
.asg A23, A_mult2_b ; 1, 2, 1, 0
.asg B21, B_mult2_b ; 1, 2, 1, 0
.asg A18, A_f2 ; 2, 2, 2, 2
.asg B16, B_f2 ; 2, 2, 2, 2
.asg A19, A_f1 ; 1, 1, 1, 1
.asg B17, B_f1 ; 1, 1, 1, 1
* ================= SYMBOLIC REGISTER ASSIGNMENTS: TEMPORARY REGISTERS ==== *
.asg A28, A_t1
.asg A7, A_t2
.asg A25, A_t3
.asg A25, A_t4
.asg A24, A_t5
.asg A5, A_t6
.asg B27, B_t1
.asg B26, B_t2
.asg B6, B_t3
.asg B24, B_t4
.asg B22, B_t5
.asg B1, B_t6
.asg A7, A_t7
.asg A26, A_t8
.asg A3, A_t9
.asg A29, A_t10
.asg A28, A_t11
.asg A0, A_t12
.asg B7, B_t7
.asg B29, B_t8
.asg B24, B_t9
.asg B4, B_t10
.asg B2, B_t11
.asg B4, B_t12
.asg A29, A_b10_h
.asg A28, A_b10_l
.asg A25, A_b11_h
.asg A24, A_b11_l
.asg A25, A_b12_h
.asg A24, A_b12_l
.asg B23, B_b13_h
.asg B22, B_b13_l
.asg B29, B_b14_h
.asg B28, B_b14_l
.asg B23, B_b15_h
.asg B22, B_b15_l
.asg A0, A_u1
.asg A26, A_u2
.asg A5, A_u3
.asg A26, A_b1
.asg A1, A_u4
.asg A1, A_u5
.asg A2, A_u6
.asg A6, A_b2
.asg B4, B_u1
.asg B22, B_u2
.asg B7, B_u3
.asg B30, B_b3
.asg B30, B_u4
.asg B22, B_u5
.asg B1, B_u6
.asg B6, B_b4
.asg A24, A_u7
.asg A30, A_u8
.asg A24, A_b5
.asg A29, A_u9
.asg A3, A_u10
.asg A7, A_b6
.asg B22, B_u7
.asg B23, B_u8
.asg B28, B_b7
.asg B23, B_u9
.asg B5, B_u10
.asg B5, B_b8
.asg A6, A_u11
.asg B6, B_u11
.asg A6, A_u12
.asg B5, B_u12
* ================= SYMBOLIC REGISTER ASSIGNMENTS: INTERMEDIATE RESULTS === *
.asg A25, A_H ; horizontal mask
.asg B6, B_H3
.asg A3, A_H5
.asg B5, B_H7
.asg A6, A_V2 ; vertical mask
.asg B2, B_V4
.asg A0, A_V6
.asg B25, B_V8
* ================= SYMBOLIC REGISTER ASSIGNMENTS: FINAL RESULTS ========== *
.asg B24, B_r13
.asg B25, B_r14
.asg A7, A_r9
.asg B23, B_r10
.asg A5, A_r11
.asg B25, B_r12
* ================= SYMBOLIC REGISTER ASSIGNMENTS: EXIT CODE + LOOP COUNT = *
.asg B24, B_r15
.asg B25, B_r16
.asg A9, A_cnt
* ========================================================================= *
* =========================== PIPE LOOP PROLOG ============================ *
SHR .S1 A_w, 3, A_wD8 ; line+1
|| SHR .S2X A_w, 2, B_wD4 ; line+2
|| SUB .L2 B_h, 2, B_h
|| ADD .L1X B_out, 1, A_out
ADD .L2X A_in, 2, B_in
|| MVC .S2 CSR, B_csr ; Remember CSR
MVKL .S1 0xFEFF, A_mult1
|| MVKL .S2 0x0202, B_f2
|| MV .D2X A_wD8, B_wD8
|| AND .L2 B_csr, -2, B_no_gie ; Clear GIE
|| LDNDW .D1T1 *+A_in[A_wD8], A_in2_l2:A_in2_l ;[ 1,1]
MPYU .M1X A_w, B_h, A_cnt
|| MVKLH .S1 0x00FF, A_mult1
|| MVKLH .S2 0x0202, B_f2
|| LDNDW .D *+B_in[B_wD8], B_in2_h2:B_in2_h ;[ 2,1]
MVKL .S1 0xFF00, A_mult1_b
|| MVKL .S2 0x0100, B_mult2_b
|| STW .D2T2 B_csr, *B_SP--[2] ; Save csr
MVKLH .S1 0xFFFE, A_mult1_b
|| MVKLH .S2 0x0102, B_mult2_b
|| MV .L1X B_wD4, A_wD4
|| LDNDW .D *+B_in[B_wD4], B_tmp4:B_tmp3 ;[ 4,1]
|| MV .L2X A_mult1, B_mult1
MVKL .S2 0x0201, B_mult2
|| MV .L1X B_f2, A_f2
|| LDNDW .D1T1 *+A_in[A_wD4], A_in3_h:A_in3_l ;[ 5,1]
MVKLH .S2 0x0001, B_mult2
|| LDNDW .D *B_in++, B_tmp2:B_tmp1 ;[ 6,1]
|| MV .L2X A_mult1_b, B_mult1_b
|| MV .L1X B_mult2_b, A_mult2_b
|| B .S1 instr1
SHRU .S1 A_cnt, 3, A_cnt
|| MVKL .S2 0x0101, B_f1
|| MPYU4 .M2 B_in2_h, B_f2, B_b13_h:B_b13_l ;[ 7,1]
|| LDNDW .D1T1 *A_in++, A_in1_h:A_in1_l ;[ 7,1]
SUB .L1 A_cnt, 2, A_cnt
|| MV .S1X B_mult2, A_mult2
|| MVKLH .S2 0x0101, B_f1
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