📄 sobel1.asm
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;******************************************************************************
;* TMS320C6x C/C++ Codegen PC Version 4.32 *
;* Date/Time created: Wed Apr 04 08:50:10 2007 *
;******************************************************************************
;******************************************************************************
;* GLOBAL FILE PARAMETERS *
;* *
;* Architecture : TMS320C64xx *
;* Optimization : Enabled at level 3 *
;* Optimizing for : Speed *
;* Based on options: -o3, no -ms *
;* Endian : Little *
;* Interrupt Thrshld : Disabled *
;* Memory Model : Small *
;* Calls to RTS : Near *
;* Pipelining : Enabled *
;* Speculative Load : Disabled *
;* Memory Aliases : Presume are aliases (pessimistic) *
;* Debug Info : COFF Debug *
;* *
;******************************************************************************
.asg A15, FP
.asg B14, DP
.asg B15, SP
.global $bss
.file "serial_asm"
* ------------------------------------------------------------------------- *
* Copyright (c) 2002 Texas Instruments, Incorporated. *
* All Rights Reserved. *
* ========================================================================= *
.text
.global _IMG_sobel1
.sect ".text"
.file "sobel1.sa"
.sym _IMG_sobel1,_IMG_sobel1, 32, 3, 0
.func 8
;******************************************************************************
;* FUNCTION NAME: _IMG_sobel1 *
;* *
;* Regs Modified : A0,A1,A2,A3,A4,A5,A6,A7,A8,A9,A10,A11,B0,B1,B2,B3,B4,*
;* B5,B6,B7,B8,B9,B10,B11,SP,A16,A17,A18,A19,A20, *
;* A21,A22,A23,A24,A25,A26,A27,A28,A29,A30,A31,B16, *
;* B17,B18,B19,B20,B21,B22,B23,B24,B25,B26,B27,B28, *
;* B29,B30,B31 *
;* Regs Used : A0,A1,A2,A3,A4,A5,A6,A7,A8,A9,A10,A11,B0,B1,B2,B3,B4,*
;* B5,B6,B7,B8,B9,B10,B11,DP,SP,A16,A17,A18,A19,A20,*
;* A21,A22,A23,A24,A25,A26,A27,A28,A29,A30,A31,B16, *
;* B17,B18,B19,B20,B21,B22,B23,B24,B25,B26,B27,B28, *
;* B29,B30,B31 *
;******************************************************************************
;******************************************************************************
;* *
;* Using -g (debug) with optimization (-o3) may disable key optimizations! *
;* *
;******************************************************************************
_IMG_sobel1:
;** --------------------------------------------------------------------------*
.line 1
.sym A_in1,4, 4, 4, 32
.sym A_in2,20, 4, 4, 32
.sym A_in3,6, 4, 4, 32
.sym B_out,22, 4, 4, 32
.sym A_w,8, 4, 4, 32
; _IMG_sobel1: .cproc A_in1, A_in2,A_in3, B_out, A_w;, B_h
; .no_mdep
.sym B_in1,53, 4, 4, 32
.sym B_in2,55, 4, 4, 32
.sym B_in3,56, 4, 4, 32
.sym A_out,57, 4, 4, 32
; .reg B_in1, B_in2,B_in3,A_out
.sym A_mult1,42, 4, 4, 32
.sym A_mult2,43, 4, 4, 32
.sym A_mult1_b,44, 4, 4, 32
.sym A_mult2_b,49, 4, 4, 32
; .reg A_mult1, A_mult2, A_mult1_b, A_mult2_b
.sym B_mult1,42, 4, 4, 32
.sym B_mult2,43, 4, 4, 32
.sym B_mult1_b,44, 4, 4, 32
.sym B_mult2_b,49, 4, 4, 32
; .reg B_mult1, B_mult2, B_mult1_b, B_mult2_b
.sym A_f1,46, 4, 4, 32
.sym A_f2,50, 4, 4, 32
; .reg A_f1, A_f2
.sym B_f1,46, 4, 4, 32
.sym B_f2,50, 4, 4, 32
; .reg B_f1, B_f2
.sym "A_in1_h:A_in1_l",3, 4, 4, 32
.sym A_in1_l,3, 4, 4, 32
.sym A_in1_h,3, 4, 4, 32
; .reg A_in1_h:A_in1_l ; |x|x|x|x|x|x|x|x| | |
.sym "B_tmp2:B_tmp1",3, 4, 4, 32
.sym B_tmp1,3, 4, 4, 32
.sym B_tmp2,3, 4, 4, 32
; .reg B_tmp2:B_tmp1 ; | | |x|x|x|x|x|x|x|x|
.sym "A_in2_l2:A_in2_l",3, 4, 4, 32
.sym A_in2_l,3, 4, 4, 32
.sym A_in2_l2,3, 4, 4, 32
; .reg A_in2_l2:A_in2_l ; |x|x|x|x|x|x|x|x| | |
.sym "B_in2_h2:B_in2_h",3, 4, 4, 32
.sym B_in2_h,3, 4, 4, 32
.sym B_in2_h2,3, 4, 4, 32
; .reg B_in2_h2:B_in2_h ; | | |x|x|x|x|x|x|x|x|
.sym "A_in3_h:A_in3_l",3, 4, 4, 32
.sym A_in3_l,3, 4, 4, 32
.sym A_in3_h,3, 4, 4, 32
; .reg A_in3_h:A_in3_l ; |x|x|x|x|x|x|x|x| | |
.sym "B_tmp4:B_tmp3",3, 4, 4, 32
.sym B_tmp3,3, 4, 4, 32
.sym B_tmp4,3, 4, 4, 32
; .reg B_tmp4:B_tmp3 ; | | |x|x|x|x|x|x|x|x|
.sym A_t1,3, 4, 4, 32
.sym A_t2,3, 4, 4, 32
.sym A_t3,3, 4, 4, 32
.sym A_t4,3, 4, 4, 32
.sym A_t5,3, 4, 4, 32
.sym A_t6,3, 4, 4, 32
.sym A_t7,3, 4, 4, 32
.sym A_t8,3, 4, 4, 32
.sym A_t9,3, 4, 4, 32
.sym A_t10,3, 4, 4, 32
; .reg A_t1, A_t2, A_t3, A_t4, A_t5, A_t6, A_t7, A_t8, A_t9, A_t10
.sym A_t11,3, 4, 4, 32
.sym A_t12,3, 4, 4, 32
; .reg A_t11, A_t12
.sym B_t1,3, 4, 4, 32
.sym B_t2,3, 4, 4, 32
.sym B_t3,3, 4, 4, 32
.sym B_t4,3, 4, 4, 32
.sym B_t5,3, 4, 4, 32
.sym B_t6,3, 4, 4, 32
.sym B_t7,3, 4, 4, 32
.sym B_t8,3, 4, 4, 32
.sym B_t9,3, 4, 4, 32
.sym B_t10,3, 4, 4, 32
; .reg B_t1, B_t2, B_t3, B_t4, B_t5, B_t6, B_t7, B_t8, B_t9, B_t10
.sym B_t11,3, 4, 4, 32
.sym B_t12,3, 4, 4, 32
; .reg B_t11, B_t12
.sym A_H,3, 4, 4, 32
.sym B_H3,3, 4, 4, 32
.sym A_H5,3, 4, 4, 32
.sym B_H7,3, 4, 4, 32
; .reg A_H, B_H3, A_H5, B_H7
.sym A_V2,3, 4, 4, 32
.sym B_V4,3, 4, 4, 32
.sym A_V6,3, 4, 4, 32
.sym B_V8,3, 4, 4, 32
; .reg A_V2, B_V4, A_V6, B_V8
.sym A_b1,3, 4, 4, 32
.sym A_b2,3, 4, 4, 32
.sym A_b3,3, 4, 4, 32
.sym A_b4,3, 4, 4, 32
.sym A_b5,3, 4, 4, 32
.sym A_b6,3, 4, 4, 32
; .reg A_b1, A_b2, A_b3, A_b4, A_b5, A_b6
.sym A_u1,3, 4, 4, 32
.sym A_u2,3, 4, 4, 32
.sym A_u3,3, 4, 4, 32
.sym A_u4,3, 4, 4, 32
.sym A_u5,3, 4, 4, 32
.sym A_u6,3, 4, 4, 32
.sym A_u7,3, 4, 4, 32
.sym A_u8,3, 4, 4, 32
.sym A_u9,3, 4, 4, 32
.sym A_u10,3, 4, 4, 32
; .reg A_u1, A_u2, A_u3, A_u4, A_u5, A_u6, A_u7, A_u8, A_u9, A_u10
.sym A_u11,3, 4, 4, 32
.sym A_u12,3, 4, 4, 32
; .reg A_u11, A_u12
.sym B_b1,3, 4, 4, 32
.sym B_b2,3, 4, 4, 32
.sym B_b3,3, 4, 4, 32
.sym B_b4,3, 4, 4, 32
.sym B_b5,3, 4, 4, 32
.sym B_b6,3, 4, 4, 32
.sym B_b7,3, 4, 4, 32
.sym B_b8,3, 4, 4, 32
; .reg B_b1, B_b2, B_b3, B_b4, B_b5, B_b6, B_b7, B_b8
.sym B_u1,3, 4, 4, 32
.sym B_u2,3, 4, 4, 32
.sym B_u3,3, 4, 4, 32
.sym B_u4,3, 4, 4, 32
.sym B_u5,3, 4, 4, 32
.sym B_u6,3, 4, 4, 32
.sym B_u7,3, 4, 4, 32
.sym B_u8,3, 4, 4, 32
.sym B_u9,3, 4, 4, 32
.sym B_u10,3, 4, 4, 32
; .reg B_u1, B_u2, B_u3, B_u4, B_u5, B_u6, B_u7, B_u8, B_u9, B_u10
.sym B_u11,3, 4, 4, 32
.sym B_u12,3, 4, 4, 32
; .reg B_u11, B_u12
.sym "A_b10_h:A_b10_l",3, 4, 4, 32
.sym A_b10_l,3, 4, 4, 32
.sym A_b10_h,3, 4, 4, 32
.sym "A_b11_h:A_b11_l",3, 4, 4, 32
.sym A_b11_l,3, 4, 4, 32
.sym A_b11_h,3, 4, 4, 32
.sym "A_b12_h:A_b12_l",3, 4, 4, 32
.sym A_b12_l,3, 4, 4, 32
.sym A_b12_h,3, 4, 4, 32
; .reg A_b10_h:A_b10_l, A_b11_h:A_b11_l, A_b12_h:A_b12_l
.sym "B_b14_h:B_b14_l",3, 4, 4, 32
.sym B_b14_l,3, 4, 4, 32
.sym B_b14_h,3, 4, 4, 32
.sym "B_b15_h:B_b15_l",3, 4, 4, 32
.sym B_b15_l,3, 4, 4, 32
.sym B_b15_h,3, 4, 4, 32
.sym "B_b13_h:B_b13_l",3, 4, 4, 32
.sym B_b13_l,3, 4, 4, 32
.sym B_b13_h,3, 4, 4, 32
; .reg B_b14_h:B_b14_l, B_b15_h:B_b15_l, B_b13_h:B_b13_l
.sym A_r9,3, 4, 4, 32
.sym B_r10,3, 4, 4, 32
.sym A_r11,3, 4, 4, 32
.sym B_r12,3, 4, 4, 32
.sym "B_r14:B_r13",6, 4, 4, 32
.sym B_r13,6, 4, 4, 32
.sym B_r14,7, 4, 4, 32
.sym B_r15,3, 4, 4, 32
.sym B_r16,3, 4, 4, 32
; .reg A_r9, B_r10, A_r11, B_r12, B_r14:B_r13, B_r15, B_r16
.sym A_cnt,21, 4, 4, 32
; .reg A_cnt ; Loop counter
.sym B_final,16, 4, 4, 32
; .reg B_final
; loop: .trip 4
STW .D2T2 B11,*SP--(24) ; |8|
STW .D2T2 B10,*+SP(20) ; |8|
STW .D2T2 B3,*+SP(16) ; |8|
STDW .D2T1 A11:A10,*+SP(8) ; |8|
.line 58
MVKL .S1 0xfeff,A21 ; |65|
.line 59
MVKLH .S1 0xff,A21 ; |66| 0, -1, -2, -1
.line 60
.line 62
MVKL .S1 0x201,A22 ; |69|
.line 63
MVKLH .S1 0x1,A22 ; |70| 0, 1, 2, 1
.line 64
.line 66
MVKL .S1 0xff00,A23 ; |73|
.line 67
MVKLH .S1 0xfffe,A23 ; |74| -1, -2, -1, 0
.line 68
.line 70
MVKL .S1 0x100,A28 ; |77|
.line 71
MVKLH .S1 0x102,A28 ; |78| 1, 2, 1, 0
.line 72
.line 74
MVKL .S1 0x101,A25 ; |81|
.line 75
MVKLH .S1 0x101,A25 ; |82| 1, 1, 1, 1
.line 76
.line 78
MVKL .S1 0x202,A29 ; |85|
.line 79
MVKLH .S1 0x202,A29 ; |86| 2, 2, 2, 2
.line 80
.line 89
.line 90
SHRU .S1 A8,0x3,A3 ; |97|
.line 91
NOP 1
MV .D2X A3,B0 ; |98|
.line 92
ADD .D2X 0xfffffffe,A3,B5 ; |99|
.line 94
ADD .D2X 0x2,A4,B16 ; |101|
.line 95
ADD .D2 0x2,B4,B18 ; |102|
.line 96
ADD .D2X 0x2,A6,B19 ; |103|
.line 97
ADD .D2 0x1,B6,B20 ; |104|
.line 102
MV .D1 A6,A24
MV .S1 A4,A26
|| LDNDW .D1T1 *A24++(8),A5:A4 ; |111| (P) <0,0> A load, line 3
LDNDW .D2T2 *B19++(8),B9:B8 ; |115| (P) <0,3> B load, line 3
LDNDW .D2T2 *B18++(8),B7:B6 ; |116| (P) <0,4> B load, line 2
MV .D1X B4,A20
MVC .S2 CSR,B11
|| LDNDW .D1T1 *A20++(8),A17:A16 ; |112| (P) <0,6> A load, line 2
MV .D2X A28,B25
|| AND .S2 -2,B11,B4
|| LDNDW .D1T1 *A26++(8),A9:A8 ; |113| (P) <0,1> A load, line 1
|| DOTPSU4 .M1 A28,A5,A7 ; |145| (P) <0,7>
SUB .L2 B5,3,B23
|| MVC .S2 B4,CSR ; interrupts off
|| LDNDW .D2T2 *B16++(8),B5:B4 ; |117| (P) <0,5> B load, line 1
|| DOTPSU4 .M1 A22,A5,A6 ; |146| (P) <0,6>
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