modmule_verilog.v

实现乘法后取模运算

/**********TopScientic**********/
/*      Version:1.0            */
/*      Date: 07/05/14         */
/*      Author:RSxia           */
/*******************************/

module modmult(mpand,mplier,modulus,product,clk,ds,reset,ready);

	parameter MPWID  = 128;
   //parameter Exp_LENGTH = 512;
   parameter MOD_LENGTH = 1024;
	
	
	input	clk,ds,reset;
	input [MPWID-1:0]	mpand;
	input [MPWID-1:0]	mplier;
	
	/*note:modular length */
	input [MOD_LENGTH-1:0] modulus;
	
	output ready;
	output[MPWID-1:0] product;
	

	reg   first;
	reg [MPWID-1:0] mpreg;
	reg [MPWID+1:0] prodreg;
	reg [MPWID+1:0] mcreg;
	reg [MPWID+1:0] modreg1,modreg2;
	wire[MPWID+1:0] mcreg1,mcreg2;

	wire reset;
	wire [MPWID-1:0] mpand;
	wire [MPWID-1:0] mplier;
	wire [MOD_LENGTH-1:0] modulus;
	
	wire  [1:0]	modstate;
	//reg ready;
	wire [MPWID-1:0] product;
	wire [MPWID+1:0] prodreg1,prodreg2,prodreg3,prodreg4;
	
	
	
	
	assign product = prodreg4[MPWID-1:0];
	
	assign prodreg1 = (mpreg[0]==1'b1)?(prodreg+mcreg):prodreg;
	
	assign prodreg2 = prodreg1- modreg1;
	assign prodreg3 = prodreg1 - modreg2;
	
	assign modstate = {prodreg3[MPWID+1],prodreg2[MPWID+1]};
	assign prodreg4 =(modstate==2'b11)? prodreg1:(modstate==2'b10)?prodreg2:prodreg3;
	assign mcreg1 = mcreg - modreg1;
	assign mcreg2 = mcreg1[MPWID]? mcreg:mcreg1;
	assign ready = first;
	
	always@(posedge clk  or negedge reset)
	begin
   if (!reset)
    begin
      first = 1'b1;
      end
   else 
    begin
     if (first) 
    	 begin
		     	if(ds)
		     	begin
		     		mpreg = mplier;//first,set multiplier to mpreg
		     		mcreg ={2'b00,mpand};//first,set multiplicand to mcreg
		     		modreg1={2'b00,modulus};//set modulus to modreg1
		     		modreg2={1'b0,modulus,1'b0};//set modulus*2 to modreg2
		     		prodreg = 0;
		     		first = 0;
	     		end
     		end
     else
     	begin
     		if(mpreg == 0)
     			begin
     				first = 1'b1;
     				end
     		else
     			begin
     				mcreg = {mcreg2[MPWID:0],1'b0};
     				mpreg = {1'b0,mpreg[MPWID-1 :1]};
     				prodreg = prodreg4;
     				end
     	end
   end
   end
  endmodule