t2t.map.summary

来自「用VHDL实现的通信滑码处理」· SUMMARY 代码 · 共 13 行

Analysis & Synthesis Status : Successful - Fri May 25 11:01:10 2007
Quartus II Version : 5.1 Build 176 10/26/2005 SJ Web Edition
Revision Name : T2T
Top-level Entity Name : T2T
Family : Stratix
Total logic elements : 58
Total pins : 10
Total virtual pins : 0
Total memory bits : 128
DSP block 9-bit elements : 0
Total PLLs : 0
Total DLLs : 0