scancode.h

TMS320C6713的16kCVSD编解码

//定义小键盘每个按键的地址
#define SCANCODE_0 0x70
#define SCANCODE_1 0x69
#define SCANCODE_2 0x72
#define SCANCODE_3 0x7A
#define SCANCODE_4 0x6B
#define SCANCODE_5 0x73
#define SCANCODE_6 0x74
#define SCANCODE_7 0x6C
#define SCANCODE_8 0x75
#define SCANCODE_9 0x7D
#define SCANCODE_Del 0x49
#define SCANCODE_Enter 0x5A
#define SCANCODE_Plus 0x79
#define SCANCODE_Minus 0x7B
#define SCANCODE_Mult 0x7C
#define SCANCODE_Divid 0x4A
#define SCANCODE_Num 0x77

/*--------------------------------------------------------------*/
/* C6713 PLL SUPPORT                                            */
/*--------------------------------------------------------------*/
#define PLL_BASE_ADDR   0x01b7c000
#define PLL_PID         ( PLL_BASE_ADDR + 0x000 )
#define PLL_CSR         ( PLL_BASE_ADDR + 0x100 )//PLL Control/Status Register
#define PLL_MULT        ( PLL_BASE_ADDR + 0x110 )
#define PLL_DIV0        ( PLL_BASE_ADDR + 0x114 )
#define PLL_DIV1        ( PLL_BASE_ADDR + 0x118 )
#define PLL_DIV2        ( PLL_BASE_ADDR + 0x11C )
#define PLL_DIV3        ( PLL_BASE_ADDR + 0x120 )
#define PLL_OSCDIV1     ( PLL_BASE_ADDR + 0x124 )

#define CSR_PLLEN          0x00000001
#define CSR_PLLPWRDN       0x00000002
#define CSR_PLLRST         0x00000008 
#define CSR_PLLSTABLE      0x00000040
#define DIV_ENABLE         0x00008000

reset_pll()
{
	/* Set the PLL back to power on reset state*/
    *(int *)PLL_CSR     = 0x00000048;
    *(int *)PLL_DIV3    = 0x00008001;
    *(int *)PLL_DIV2    = 0x00008001;
    *(int *)PLL_DIV1    = 0x00008000;
    *(int *)PLL_DIV0    = 0x00008000;
    *(int *)PLL_MULT    = 0x00000007;
    *(int *)PLL_MULT    = 0x00000007;
    *(int *)PLL_OSCDIV1 = 0x00080007;           
}

init_pll()
{
    /* When PLLEN is off DSP is running with CLKIN clock source,
    * currently 50MHz or 20ns clk rate.
    */
    *(int *)PLL_CSR  &= ~CSR_PLLEN;

    /* Reset the pll.  PLL takes 125ns to reset.    */
    *(int *)PLL_CSR  |= CSR_PLLRST;

    /* PLLOUT = CLKIN/(DIV0+1) * PLLM
    * 400    = 50/1 * 8//9
    */ 
    *(int *)PLL_DIV0    = DIV_ENABLE + 0;  
    *(int *)PLL_MULT    = 8;//9;               


    *(int *)PLL_OSCDIV1 = DIV_ENABLE + 4;

    /* Program in reverse order. 
    *  DSP requires that pheriheral clocks be less then
    *  1/2 the CPU clock at all times.
    */

    *(int *)PLL_DIV3    = DIV_ENABLE + 3; //1/5

    *(int *)PLL_DIV2    = DIV_ENABLE + 1; //1/4

    *(int *)PLL_DIV1    = DIV_ENABLE + 1; //1/2
    
    *(int *)PLL_CSR  &= ~CSR_PLLRST;

	/* Now enable pll path and we are off and running at 200MHz
	* with 80 MHz SDRAM.
	*/
    *(int *)PLL_CSR |= CSR_PLLEN;

}
/*定义初始化系统时钟的寄存器
#define PLLCSR 0x01B7C100
#define PLLM_Register 0x01B7C110
#define PLLDIV0 0x01B7C114
#define PLLDIV1 0x01B7C118
#define PLLDIV2 0x01B7C11C
#define PLLDIV3 0x01B7C120
#define OSCDIV1_Register 0x01B7C124
*/