smg3.vhd

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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity smg3 is
port(clk,rst: in std_logic;
myout:out std_logic_vector(6 downto 0);
cp:out std_logic_vector(5 downto 0));

end smg3;
architecture timer of smg3 is
signal  tmp:std_logic_vector(5 downto 0);
signal   num:std_logic_vector(2 downto 0);
begin process(clk,rst)
begin 
if rst='1' then tmp<="111111" ; num<="000";
elsif clk'event and clk='1' 
then
   num<=num+1; 
  if num="110" then num<="000";
end if;
end if;
case num is
when "000"=>tmp<="111111";myout<="0000000";
when "001"=>tmp<="011111";myout<="1111110";
when "010"=>tmp<="101111";myout<="0110000";
when "011"=>tmp<="110111";myout<="1101101";
when "100"=>tmp<="111011";myout<="1111001";
when "101"=>tmp<="111101";myout<="0110011";
when "110"=>tmp<="111110";myout<="1011011";
when others =>null;
end case;
cp<=tmp;




end process;

end timer;