eth860.h

ertfs文件系统里面既有完整ucos程序

#define SCCM_TRANS_RCH    0x0008
#define SCCM_TRANS_TXE    0x0010
#define SCCM_TRANS_GRA    0x0080
#define SCCM_TRANS_DCC    0x0400
#define SCCM_TRANS_GLT    0x0800
#define SCCM_TRANS_GLR    0x1000

#define SCCS_TRANS_CS     0x20

#define GSMR_H_GDE           0x00010000
#define GSMR_H_TCRC_16       0x00000000
#define GSMR_H_TCRC_CRC16    0x00004000
#define GSMR_H_TCRC_32       0x00008000
#define GSMR_H_REVD          0x00002000
#define GSMR_H_TRX           0x00001000
#define GSMR_H_TTX           0x00000800
#define GSMR_H_CDP           0x00000400
#define GSMR_H_CTSP          0x00000200
#define GSMR_H_CDS           0x00000100
#define GSMR_H_CTSS          0x00000080
#define GSMR_H_TFL           0x00000040
#define GSMR_H_RFW           0x00000020
#define GSMR_H_TXSY          0x00000010
#define GSMR_H_SYNL_EXT      0x00000000
#define GSMR_H_SYNL_4        0x00000004
#define GSMR_H_SYNL_8        0x00000008
#define GSMR_H_SYNL_16       0x0000000c
#define GSMR_H_RTSM          0x00000002
#define GSMR_H_RSYN          0x00000001
#define GSMR_L_EDGE_BOTH     0x00000000
#define GSMR_L_EDGE_POS      0x20000000
#define GSMR_L_EDGE_NEG      0x40000000
#define GSMR_L_EDGE_NONE     0x60000000
#define GSMR_L_TCI           0x10000000
#define GSMR_L_TSNC_INF      0x00000000
#define GSMR_L_TSNC_14       0x04000000
#define GSMR_L_TSNC_4        0x08000000
#define GSMR_L_TSNC_3        0x0c000000
#define GSMR_L_RINV          0x02000000
#define GSMR_L_TINV          0x01000000
#define GSMR_L_TPL_NONE      0x00000000
#define GSMR_L_TPL_8         0x00200000
#define GSMR_L_TPL_16        0x00400000
#define GSMR_L_TPL_32        0x00600000
#define GSMR_L_TPL_48        0x00800000
#define GSMR_L_TPL_64        0x00a00000
#define GSMR_L_TPL_128       0x00c00000
#define GSMR_L_TPP_00        0x00000000
#define GSMR_L_TPP_10        0x00080000
#define GSMR_L_TPP_01        0x00100000
#define GSMR_L_TPP_11        0x00180000
#define GSMR_L_TEND          0x00040000
#define GSMR_L_TDCR_1        0x00000000
#define GSMR_L_TDCR_8        0x00010000
#define GSMR_L_TDCR_16       0x00020000
#define GSMR_L_TDCR_32       0x00030000
#define GSMR_L_RDCR_1        0x00000000
#define GSMR_L_RDCR_8        0x00004000
#define GSMR_L_RDCR_16       0x00008000
#define GSMR_L_RDCR_32       0x0000c000
#define GSMR_L_RENC_NRZ      0x00000000
#define GSMR_L_RENC_NRZI     0x00000800
#define GSMR_L_RENC_FM0      0x00001000
#define GSMR_L_RENC_MAN      0x00002000
#define GSMR_L_RENC_DIF      0x00003000
#define GSMR_L_TENC_NRZ      0x00000000
#define GSMR_L_TENC_NRZI     0x00000100
#define GSMR_L_TENC_FM0      0x00000200
#define GSMR_L_TENC_MAN      0x00000400
#define GSMR_L_TENC_DIF      0x00000600
#define GSMR_L_DIAG_NORM     0x00000000
#define GSMR_L_DIAG_LOOPBACK 0x00000040
#define GSMR_L_DIAG_ECHO     0x00000080
#define GSMR_L_DIAG_BOTH     0x000000c0
#define GSMR_L_ENR           0x00000020
#define GSMR_L_ENT           0x00000010
#define GSMR_L_MODE_HDLC     0x00000000
#define GSMR_L_MODE_LOCAL    0x00000002
#define GSMR_L_MODE_SS7      0x00000003
#define GSMR_L_MODE_UART     0x00000004
#define GSMR_L_MODE_PROFIBUS 0x00000005
#define GSMR_L_MODE_ASYNC    0x00000006
#define GSMR_L_MODE_V14      0x00000007
#define GSMR_L_MODE_BISYNC   0x00000008
#define GSMR_L_MODE_DDCMP    0x00000009
#define GSMR_L_MODE_ETH      0x0000000c

#define PSMR_HBC            0x8000
#define PSMR_FC             0x4000
#define PSMR_RSH            0x2000
#define PSMR_IAM            0x1000
#define PSMR_CRC_32         0x0800
#define PSMR_PRO            0x0200
#define PSMR_BRO            0x0100
#define PSMR_SBT            0x0080
#define PSMR_LPB            0x0040
#define PSMR_SIP            0x0020
#define PSMR_LCW            0x0010
#define PSMR_NIB_13         0x0000
#define PSMR_NIB_14         0x0002
#define PSMR_NIB_15         0x0004
#define PSMR_NIB_16         0x0006
#define PSMR_NIB_21         0x0008
#define PSMR_NIB_22         0x000a
#define PSMR_NIB_23         0x000c
#define PSMR_NIB_24         0x000e
#define PSMR_FDE            0x0001

/* SMC general         */
#define SMCMR_LEN(len) ((unsigned short)((len) << 11))
#define SMCMR_SL       0x0400
#define SMCMR_PEN      0x0200
#define SMCMR_PM       0x0100
#define SMCMR_SM_UART  0x0020
#define SMCMR_SM_TRANS 0x0030
#define SMCMR_DM_LOOP  0x0004
#define SMCMR_DM_ECHO  0x0008
#define SMCMR_TEN      0x0002
#define SMCMR_REN      0x0001

#define SMCE_UART_BRKE 0x40
#define SMCE_UART_BRK  0x10
#define SMCE_UART_BSY  0x04
#define SMCE_UART_TX   0x02
#define SMCE_UART_RX   0x01

#define SMCM_UART_BRKE 0x40
#define SMCM_UART_BRK  0x10
#define SMCM_UART_BSY  0x04
#define SMCM_UART_TX   0x02
#define SMCM_UART_RX   0x01

/* Port A registers         */

#define PA_SCCRXD1 0x0001
#define PA_SCCTXD1 0x0002
#define PA_SCCRXD2 0x0004
#define PA_SCCTXD2 0x0008
#define PA_SCCRXD3 0x0010
#define PA_SCCTXD3 0x0020
#define PA_SCCRXD4 0x0040
#define PA_SCCTXD4 0x0080
#define PA_CLK1    0x0100
#define PA_CLK2    0x0200
#define PA_CLK3    0x0400
#define PA_CLK4    0x0800
#define PA_CLK5    0x1000
#define PA_CLK6    0x2000
#define PA_CLK7    0x4000
#define PA_CLK8    0x8000

/* Port B registers         */
#define PB_SMTXD1 0x0040         /* SMC1 tx pin */
#define PB_SMRXD1 0x0080         /* SMC1 rx pin */
#define PB_SMTXD2 0x0400         /* SMC2 tx pin */
#define PB_SMRXD2 0x0800         /* SMC2 rx pin */
#define PB_RTS1   0x1000         /* SCC1 RTS (also available in port C) */
#define PB_RTS4   0x8000         /* SCC4 RTS */

/* Port C registers         */
#define PC_SCCRTS1 0x0001
#define PC_SCCRTS2 0x0002
#define PC_SCCRTS3 0x0004
#define PC_SCCRTS4 0x0008
#define PC_SCCCTS1 0x0010
#define PC_SCCCD1  0x0020
#define PC_SCCCTS2 0x0040
#define PC_SCCCD2  0x0080
#define PC_SCCCTS3 0x0100
#define PC_SCCCD3  0x0200
#define PC_SCCCTS4 0x0400
#define PC_SCCCD4  0x0800

/* Timer registers         */

#define TGCR_CAS4 0x8000
#define TGCR_FRZ4 0x4000
#define TGCR_STP4 0x2000
#define TGCR_RST4 0x1000

#define TMR_PS(n) ((n) << 8)
#define TMR_CE_NONE    0x0000
#define TMR_CE_RISING  0x0040
#define TMR_CE_FALLING 0x0080
#define TMR_CE_ANY     0x00c0
#define TMR_OM         0x0020
#define TMR_ORI        0x0010
#define TMR_FRR        0x0008
#define TMR_ICLK_CAS   0x0000
#define TMR_ICLK_INT   0x0002
#define TMR_ICLK_INT16 0x0004
#define TMR_ICLK_TIN   0x0006
#define TMR_GE         0x0001

#define TER_REF        0x0002
#define TER_CAP        0x0001


/* BRG registers         */
#define BRGC_RST         0x00020000        /* Reset */
#define BRGC_EN          0x00010000        /* Enable */
#define BRGC_EXTC_BRGCLK 0x00000000        /* Clock comes from internal BRGCLK */
#define BRGC_EXTC_CLK2   0x00004000        /* Clock comes from CLK2 pin */
#define BRGC_EXTC_CLK6   0x00008000        /* Clock comes from CLK6 pin */
#define BRGC_ATB         0x00002000        /* Autobaud */
#define BRGC_CD(num)     ((unsigned long)(num)<<1) /* Clock divider */
#define BRGC_DIV16       0x00000001        /* Divide by 16 prescaler */

/* SI registers         */
#define SIMODE_SMC1TDM     0x00008000      /* SMC1 uses TDM */
#define SIMODE_SMC1CS_BRG1 0x00000000      /* SMC1 Clock Source */
#define SIMODE_SMC1CS_BRG2 0x00001000
#define SIMODE_SMC1CS_BRG3 0x00002000
#define SIMODE_SMC1CS_BRG4 0x00003000
#define SIMODE_SMC1CS_CLK1 0x00004000
#define SIMODE_SMC1CS_CLK2 0x00005000
#define SIMODE_SMC1CS_CLK3 0x00006000
#define SIMODE_SMC1CS_CLK4 0x00007000
#define SIMODE_SMC2TDM     0x80000000      /* SMC2 uses TDM */
#define SIMODE_SMC2CS_BRG1 0x00000000      /* SMC2 Clock Source */
#define SIMODE_SMC2CS_BRG2 0x10000000
#define SIMODE_SMC2CS_BRG3 0x20000000
#define SIMODE_SMC2CS_BRG4 0x30000000
#define SIMODE_SMC2CS_CLK5 0x40000000
#define SIMODE_SMC2CS_CLK6 0x50000000
#define SIMODE_SMC2CS_CLK7 0x60000000
#define SIMODE_SMC2CS_CLK8 0x70000000

#define SICR_R_BRG1  0x00    
#define SICR_R_BRG2  0x01
#define SICR_R_BRG3  0x02
#define SICR_R_BRG4  0x03
#define SICR_R_CLK1  0x04
#define SICR_R_CLK2  0x05
#define SICR_R_CLK3  0x06
#define SICR_R_CLK4  0x07

#define SICR_T_BRG1  0x00    
#define SICR_T_BRG2  0x08
#define SICR_T_BRG3  0x10
#define SICR_T_BRG4  0x18
#define SICR_T_CLK1  0x20
#define SICR_T_CLK2  0x28
#define SICR_T_CLK3  0x30
#define SICR_T_CLK4  0x38

#define SICR_SC      0x40
#define SICR_GR      0x80

        
#if __cplusplus
 extern "C" {
#endif

/*--------------------------------------------------------------------------
*
* FUNCTION NAME: getXXX()
*
* DESCRIPTION:
*
*     returns in R3, the current value of the special purpose control register. 
*     add more special registers as necessary.
*     use 3 instead of %r3 because it works with both meta and diab.
*
* EXTERNAL EFFECTS: None
*
* PARAMETERS: None
*
* RETURNS: special register value in R3.
*-------------------------------------------------------------------------*/
UWORD getMSR(void);   
UWORD getIMMR(void);      /* (821/860 only) in ppc_bios.s or InitPpc.c */
UWORD getICR(void);   /* (821/860 only) in ppc_bios.s or InitPpc.c */
UWORD getDER(void);   /* (821/860 only) in ppc_bios.s or InitPpc.c */
UWORD getDEC(void);
UWORD getevt(void); /* in InitPpc.c */ 
/*--------------------------------------------------------------------------
*
* MACRO NAME: setXXX()
*
* DESCRIPTION:
*
*     sets the value in specified control register. 
*     add more functions as necessary.
*     this method works for both meta and diab.
*
* EXTERNAL EFFECTS: None.
*
* PARAMETERS: value is the value to be written to the spr control reg.
*
* RETURNS: None.
*-------------------------------------------------------------------------*/
void  set_msr(UWORD value);   /* in InitPpc.c */
void  setMSR(UWORD value);        /* dont call setMSR directly, use the function set_msr() instead*/
void  setIMMR(UWORD value);       /* (821/860 only) store in Internal Memory Map register*/
void  setDER(UWORD value);        /* (821/860 only) in ppc_bios.s or InitPpc.c */
void  setDEC(UWORD value);        /* in ppc_bios.s or InitPpc.c  */


void init_ppc(void);
void ext_int_handler(void);

#if __cplusplus
}
#endif

#endif /* __HMPC860__ */