📄 eth860.h
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#define SCCR_DFNL_256 0x00000700 /* div by 256 */
#define SCCR_DFNH 0x000000C0 /* Div Factor High Freq */
#define SCCR_DFNH_1 0x00000000 /* div by 1 */
#define SCCR_DFNH_2 0x00000020 /* div by 2 */
#define SCCR_DFNH_4 0x00000040 /* div by 4 */
#define SCCR_DFNH_8 0x00000060 /* div by 8 */
#define SCCR_DFNH_16 0x00000080 /* div by 16 */
#define SCCR_DFNH_32 0x000000A0 /* div by 32 */
#define SCCR_DFNH_64 0x000000C0 /* div by 64 */
#define SCCR_USED \
( \
SCCR_COM_OEF /* Output Enab Full strngth */ \
+SCCR_TBS_OSC_DIV_4_16 /* source = osc clk div 4 or 16 */ \
+SCCR_RTDIV_DIV_4 /* RTC and PIT clock div by 4 */ \
+SCCR_RTSEL_OSCM /* source = OSCM clock */ \
+SCCR_CRQEN_LOW /* remains low freq */ \
+SCCR_PRQEN_LOW /* remains low freq */ \
+SCCR_EBDF_GCLK2_DIV_1 /* GCLK2 div by 1 */ \
+SCCR_DFSYNC_1 /* div by 1 */ \
+SCCR_DFBRG_1 /* div by 1 */ \
+SCCR_DFNL_2 /* div by 2 */ \
+SCCR_DFNH_1 /* div by 1 */ \
)
/**** End Memory-mapped registers *** */
/*---------------------------------------------------------------------------- */
/* SCC1 Interrupt Vector Code in CPM Vector Register (CIVR) (16-479) (16-485) */
/*---------------------------------------------------------------------------- */
#define PARALLEL_IO_PC15_VECTOR 0x1F
#define SCC1_VECTOR 0x1E
#define SCC2_VECTOR 0x1D
#define SCC3_VECTOR 0x1C
#define SCC4_VECTOR 0x1B
#define PARALLEL_IO_PC14_VECTOR 0x1A
#define TIMER1_VECTOR 0x19
#define PARALLEL_IO_PC13_VECTOR 0x18
#define PARALLEL_IO_PC12_VECTOR 0x17
#define SDMA_CHANNEL_ERR_VECTOR 0x16
#define IDMA1_VECTOR 0x15
#define IDMA2_VECTOR 0x14
#define RESERVED1_VECTOR 0x13
#define TIMER2_VECTOR 0x12
#define RISC_TIMER_TBL_VECTOR 0x11
#define I2C_VECTOR 0x10
#define PARALLEL_IO_PC11_VECTOR 0x0F
#define PARALLEL_IO_PC10_VECTOR 0x0E
#define RESERVED2_VECTOR 0x0D
#define TIMER3_VECTOR 0x0C
#define PARALLEL_IO_PC9_VECTOR 0x0B
#define PARALLEL_IO_PC8_VECTOR 0x0A
#define PARALLEL_IO_PC7_VECTOR 0x09
#define RESERVED3_VECTOR 0x08
#define TIMER4_VECTOR 0x07
#define PARALLEL_IO_PC6_VECTOR 0x06
#define SPI_VECTOR 0x05
#define SMC1_VECTOR 0x04
#define SMC2_VECTOR 0x03
#define PARALLEL_IO_PC5_VECTOR 0x02
#define PARALLEL_IO_PC4_VECTOR 0x01
#define ERROR_VECTOR 0x00
#if (ADS860 || FADS860) /* ADS860 board */
/* BCSR led/enable defines, See MPC860ADS manual page 56 */
#define ETHEN 0x20000000 /* ETHEN in bit 2 of BCSR1 */
#define IRDEN 0x10000000 /* ETHEN in bit 3 of BCSR1 */
#define RS232EN1 0x01000000 /* ETHEN in bit 7 of BCSR1 */
#define RS232EN2 0x00040000 /* ETHEN in bit 13 of BCSR1 */
#define PCMCIAEN 0x00800000 /* ETHEN in bit 8 of BCSR1 */
#elif (MPC860) /* MPC860 */
/* CSR led/enable defines */
#define LED4 0x08 /* 1=off, typically used for BRDFAIL */
#define LED5 0x04 /* 1=off, typically used for Battery Low */
#define LED6 0x02 /* 1=off, typically used for Flash Programming */
/* satisfy compiler with byte size values for unused enables */
#define ETHEN 0x00
#define IRDEN 0x00
#define RS232EN1 0x00
#define RS232EN2 0x00
#define PCMCIAEN 0x00
#else
#error: Please define a board type
#endif
#if (ADS860 || FADS860) /* ADS860 board */
typedef struct bcsr
{
UWORD bcsr0; /* Board Control and Status Register */
UWORD bcsr1;
UWORD bcsr2;
UWORD bcsr3;
} BCSR;
#elif (MPC860) /* MPC860 */
typedef struct bcsr
{
UBYTE bcsr1; /* Board Control and Status Register */
UBYTE bcsr2;
} BCSR;
#else
#error: Please define a board type
#endif
#define READY_TO_RX_CMD 0 /* Ready to receive a command */
typedef union
{
unsigned char bytes [6];
struct
{
unsigned long dword;
unsigned short word;
} words;
} NODE_ADDRESS;
/*---------------------------------------- */
/* Constants and Definitions for Ethernet */
/*---------------------------------------- */
#define ENET_C_PRES 0xFFFFFFFF /* CRC Preset */
#define ENET_C_MASK 0xDEBB20E3 /* Constant MASK for CRC */
#define ENET_MFLR 1518 /* Ethernet Max Frame Length */
#define ENET_MINFLR 64 /* Ethernet Min Frame Length */
#define ENET_MDMA 1520 /* Max DMA length */
#define ENET_RET_LIM 15 /* Retry Limit Threshold */
#define ENET_PAD 0x8888 /* Pad Characters */
#define ENET_DSR 0xD555 /* DSR value for Ethernet */
#define ENET_PADDR_H 0x5548; /* Physical Address 1 (MSB) */
#define ENET_PADDR 0x3322; /* Physical Address */
#define ENET_PADDR_L 0x1900; /* Physical Address 1 (LSB) */
#define TXBUFINDEX 8
/* Buffer descriptors etc. go at start of DP RAM */
#define BD_SMC_UART_RX_EMPTY 0x8000
#define BD_SMC_UART_RX_WRAP 0x2000
#define BD_SMC_UART_RX_INTERRUPT 0x1000
#define BD_SMC_UART_RX_CONTINUOUS 0x0200
#define BD_SMC_UART_RX_IDLES 0x0100
#define BD_SMC_UART_RX_BREAK 0x0020
#define BD_SMC_UART_RX_FRAMING 0x0010
#define BD_SMC_UART_RX_PARITY 0x0008
#define BD_SMC_UART_RX_OVERRUN 0x0002
#define BD_SMC_UART_RX_CARRIER 0x0001
#define BD_SMC_UART_TX_READY 0x8000
#define BD_SMC_UART_TX_WRAP 0x2000
#define BD_SMC_UART_TX_INTERRUPT 0x1000
#define BD_SMC_UART_TX_CONTINUOUS 0x0200
#define BD_SMC_UART_TX_PREAMBLE 0x0100
#define BD_SCC_ETH_RX_EMPTY 0x8000
#define BD_SCC_ETH_RX_WRAP 0x2000
#define BD_SCC_ETH_RX_INTERRUPT 0x1000
#define BD_SCC_ETH_RX_LAST 0x0800
#define BD_SCC_ETH_RX_FIRST 0x0400
#define BD_SCC_ETH_RX_MISS 0x0100
#define BD_SCC_ETH_RX_VIOLATION 0x0020
#define BD_SCC_ETH_RX_NONALIGNED 0x0010
#define BD_SCC_ETH_RX_LITTLE 0x0008
#define BD_SCC_ETH_RX_CRC 0x0004
#define BD_SCC_ETH_RX_OVERRUN 0x0002
#define BD_SCC_ETH_RX_COLLISION 0x0001
#define BD_SCC_ETH_RX_STAT_BITS 0x0fff
#define BD_SCC_ETH_TX_READY 0x8000
#define BD_SCC_ETH_TX_PAD 0x4000
#define BD_SCC_ETH_TX_WRAP 0x2000
#define BD_SCC_ETH_TX_INTERRUPT 0x1000
#define BD_SCC_ETH_TX_LAST 0x0800
#define BD_SCC_ETH_TX_CRC 0x0400
#define BD_SCC_ETH_TX_COLLISION 0x0200
#define BD_SCC_ETH_TX_HEARTBEAT 0x0100
#define BD_SCC_ETH_TX_LATE 0x0080
#define BD_SCC_ETH_TX_LIMIT 0x0040
#define BD_SCC_ETH_TX_RETRY_MASK 0x003c
#define BD_SCC_ETH_TX_RETRY(c) ((c) << 2)
#define BD_SCC_ETH_TX_UNDERRUN 0x0002
#define BD_SCC_ETH_TX_CARRIER 0x0001
#define BD_SCC_ETH_TX_STAT_BITS 0x03ff
#define BD_SCC_TRANS_RX_EMPTY 0x8000
#define BD_SCC_TRANS_RX_WRAP 0x2000
#define BD_SCC_TRANS_RX_INTERRUPT 0x1000
#define BD_SCC_TRANS_RX_LAST 0x0800
#define BD_SCC_TRANS_RX_FIRST 0x0400
#define BD_SCC_TRANS_RX_CONTINUOUS 0x0200
#define BD_SCC_TRANS_RX_DPLL 0x0080
#define BD_SCC_TRANS_RX_NONALIGNED 0x0010
#define BD_SCC_TRANS_RX_CRC 0x0004
#define BD_SCC_TRANS_RX_OVERRUN 0x0002
#define BD_SCC_TRANS_RX_CARRIER 0x0001
#define BD_SCC_TRANS_TX_READY 0x8000
#define BD_SCC_TRANS_TX_WRAP 0x2000
#define BD_SCC_TRANS_TX_INTERRUPT 0x1000
#define BD_SCC_TRANS_TX_LAST 0x0800
#define BD_SCC_TRANS_TX_CRC 0x0400
#define BD_SCC_TRANS_TX_CONTINUOUS 0x0200
#define BD_SCC_TRANS_TX_UNDERRUN 0x0002
#define BD_SCC_TRANS_TX_CTS 0x0001
#define MBAR ((unsigned long *) 0x0003ff00)
typedef struct
{
unsigned short flags;
unsigned short length;
void * buffer;
}
BUFFER_DESCRIPTOR;
/* can't cast pointer to word in diab, therefore use this union */
typedef union{
volatile BUFFER_DESCRIPTOR *bd;
UHWORD rbase[2];
UHWORD tbase[2];
}bd_union_type;
/* Buffer descriptors etc. go at start of DP RAM */
/*#define BUFFER_DESCRIPTORS ((volatile BUFFER_DESCRIPTOR *) DPRBASE) */
// #if (POWERPCEABI || POWERPCDIAB) I can't get this compiler to read the union structure
#define BUFFER_DESCRIPTORS ((volatile BUFFER_DESCRIPTOR *) IMMR_UDATA_BD)
// #endif
/*-------------------------------------------------------------------- */
/* SMC UART parameter RAM */
/*-------------------------------------------------------------------- */
typedef struct
{
UHWORD rbase; /* Rx BD Base Address */
UHWORD tbase; /* Tx BD Base Address */
UBYTE rfcr; /* Rx function code */
UBYTE tfcr; /* Tx function code */
UHWORD mrblr; /* Rx buffer length */
UWORD rstate; /* Rx internal state */
UWORD rptr; /* Rx internal data pointer */
UHWORD rbptr; /* rb BD Pointer */
UHWORD rcount; /* Rx internal byte count */
UWORD rtemp; /* Rx temp */
UWORD tstate; /* Tx internal state */
UWORD tptr; /* Tx internal data pointer */
UHWORD tbptr; /* Tx BD pointer */
UHWORD tcount; /* Tx byte count */
UWORD ttemp; /* Tx temp */
UHWORD max_idl; /* Maximum IDLE Characters */
UHWORD idlc; /* Temporary IDLE Counter */
UHWORD brkln; /* Last Rx Break Length */
UHWORD brkec; /* Rx Break Condition Counter */
UHWORD brkcr; /* Break Count Register (Tx) */
UHWORD r_mask; /* Temporary bit mask */
} SMC_UART_PRAM;
#define SMC1_PRAM ((volatile SMC_UART_PRAM *) IMMR_SMC1_PRAM)
#define SMC2_PRAM ((volatile SMC_UART_PRAM *) IMMR_SMC2_PRAM)
#define NumRxBDs 16 /* ethernet receive buffer descriptors */
#define NumTxBDs 2 /* ethernet transmit buffer descriptors */
#define SMC1RxBDs 4 /* rs232 receive buffer descriptors */
#define SMC1TxBDs 4 /* rs232 transmit buffer descriptors */
#define SMC2RxBDs 1 /* rs232 receive buffer descriptors */
#define SMC2TxBDs 1 /* rs232 transmit buffer descriptors */
#define SCC1_RX_BD 0
#define SCC1_TX_BD SCC1_RX_BD + NumRxBDs
#define SMC1_RX_BD SCC1_TX_BD + NumTxBDs
#define SMC1_TX_BD SMC1_RX_BD + SMC1RxBDs
#define SMC2_RX_BD SMC1_TX_BD + SMC1TxBDs
#define SMC2_TX_BD SMC2_RX_BD + SMC2RxBDs
/* use more Tx buffers for SMC - allow us to Q up debug messages */
/* SCC general */
#define SCCE_ETH_RXB 0x0001 /* Buffer received */
#define SCCE_ETH_TXB 0x0002 /* Buffer transmitted */
#define SCCE_ETH_BSY 0x0004 /* Busy - not enough buffers */
#define SCCE_ETH_RXF 0x0008 /* Frame received */
#define SCCE_ETH_TXE 0x0010 /* Transmit error */
#define SCCE_ETH_GRA 0x0080 /* Graceful stop complete */
#define SCCM_ETH_RXB 0x0001 /* Buffer received */
#define SCCM_ETH_TXB 0x0002 /* Buffer transmitted */
#define SCCM_ETH_BSY 0x0004 /* Busy - not enough buffers */
#define SCCM_ETH_RXF 0x0008 /* Frame received */
#define SCCM_ETH_TXE 0x0010 /* Transmit error */
#define SCCM_ETH_GRA 0x0080 /* Graceful stop complete */
#define SCCE_TRANS_RX 0x0001
#define SCCE_TRANS_TX 0x0002
#define SCCE_TRANS_BSY 0x0004
#define SCCE_TRANS_RCH 0x0008
#define SCCE_TRANS_TXE 0x0010
#define SCCE_TRANS_GRA 0x0080
#define SCCE_TRANS_DCC 0x0400
#define SCCE_TRANS_GLT 0x0800
#define SCCE_TRANS_GLR 0x1000
#define SCCM_TRANS_RX 0x0001
#define SCCM_TRANS_TX 0x0002
#define SCCM_TRANS_BSY 0x0004
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