📄 eth860.h
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/* */
/* ETH860.H */
/* */
/* EBS - RTIP */
/* */
/* Copyright Peter Van Oudenaren , 1993 */
/* All rights reserved. */
/* This code may not be redistributed in source or linkable object form */
/* without the consent of its author. */
/* */
/* */
/* Registers names ending in "_" denote 16 bit registers */
#ifndef __HMPC860__
#define __HMPC860__ 1
/* define a board type */
#define ADS860 1
#define FADS860 0
#define MPC860 0
/* define smc channel used for terminal I/O (polled debug port) and UART (interrupt port) */
#define SMC1TERM 1
#define SMC2TERM 0
#define SMC1UART 0
#define SMC2UART 0
/* define DECLARE_STORAGE_CLASS in only one place (InitPPC.c) */
#ifdef DECLARE_STORAGE_CLASS
#define STORAGE_CLASS
#define INITIAL(i) = i
#define INITSTR = ""
#else
#define STORAGE_CLASS extern
#define INITIAL(i)
#define INITSTR
#endif
#if defined (PPC)
#endif
/* defines for motorola's files mpc860.h and masks860.h */
typedef unsigned char UBYTE;
typedef unsigned short UHWORD;
typedef unsigned long UWORD;
typedef volatile unsigned char VUBYTE;
typedef volatile short VHWORD;
typedef volatile unsigned short VUHWORD;
typedef volatile unsigned long VUWORD;
#include "mpc860.h" /* IMMR definitions and declarations */
#include "masks860.h" /* Global masks header file */
STORAGE_CLASS EPPC *IMMR; /* IMMR base pointer */
#define DISABLE8XX() __asm (" mtspr 81, 0 "); /* EID reg (505 & 800 core specific) writing anything to this reg clears EE & sets RI */
#define ENABLE8XX() __asm (" mtspr 80, 0 "); /* EIE reg (505 & 800 core specific) writing anything to this reg sets EE & RI */
/**** Board-Specific Definitions *** */
#if (ADS860 || FADS860) /* ADS860 boards */
#define SYS_CLK_FREQ 24000000 /* 24 MHz System Clock */
#define SYS_DIV_FOR_BG 16 /* clock divide for baudrate gen */
#elif (MPC860) /* MPC860 */
#define SYS_CLK_FREQ 50000000 /* 50 MHz System Clock */
#define SYS_DIV_FOR_BG 16 /* clock divide for baudrate gen */
#else
#error: Please define a board type
#endif
/**** Define baud rate generator settings for common baud rates ****/
/* see Baud Rate Generator Configuration Register definitions 16-141 */
#if(ADS860 || FADS860)
/* clock: @24 Mhz */
#define B1200 0x109C2 /* 1200 baud */
#define B2400 0x104E0 /* 2400 baud */
#define B9600 0x10136 /* 9600 baud */
#define B19200 0x1009A /* 19200 baud */
#define B38400 0x1004C /* 38400 baud */
#define B57600 0x10032 /* 57600 baud */
#define B115400 0x10018 /* 115400 baud */
#elif(MPC860)
/* clock: @50 Mhz */
#define B1200 0x11456 /* 1200 baud */
#define B2400 0x10A2A /* 2400 baud */
#define B9600 0x1028A /* 9600 baud */
#define B19200 0x10144 /* 19200 baud */
#define B38400 0x100A0 /* 38400 baud */
#define B57600 0x1006A /* 57600 baud */
#define B115400 0x10034 /* 115400 baud */
#else
#error
#endif
/**** SPR's (Special Purpose registers) *** */
#define XER 1 /* fixed-point exception cause register */
#define LR 8 /* Link Register */
#define CTR 9 /* Count register */
#define DEC 22 /* Decrementer Register */
#define SRR0 26 /* machine Status Save/Rest */
#define SRR1 27 /* machine/Status Save/Rest */
#define EIE 80 /* External Interrupt Enable */
#define EID 81 /* External Interrupt Disable */
#define ICR 148 /* Interrupt Cause Register */
#define DER 149 /* Debug Enable Register */
#define DER_RSTE 0x40000000 /* Reset Interrupt Enable */
#define DER_CHSTPE 0x20000000 /* Check Stop Enable */
#define DER_MCIE 0x10000000 /* Machine Check Interrupt Enable */
#define DER_EXTIE 0x02000000 /* External Interrupt Enable */
#define DER_ALIE 0x01000000 /* Alignment Interrupt Enable */
#define DER_PRIE 0x00800000 /* Program Interrupt Enable */
#define DER_FPUVIE 0x00400000 /* Floating Point Unavail Int Enab */
#define DER_DECIE 0x00200000 /* Decrementer Interrupt Enable */
#define DER_SYSIE 0x00040000 /* System Call Interrupt Enable */
#define DER_TRE 0x00020000 /* Trace Interrupt Enable */
#define DER_SEIE 0x00004000 /* Software Emulation Intrpt Enab */
#define DER_ITLBMSE 0x00002000 /* Impl-Specific Instr TLB Miss Intrpt Enab */
#define DER_ITLBERE 0x00001000 /* Impl-Spec Instr TLB Error Enab */
#define DER_DTLBMSE 0x00000800 /* Impl-Spec Data TLB Miss Enab */
#define DER_DTLBERE 0x00000400 /* Impl-Spec Data TLB Error Enab */
#define DER_LBRKE 0x00000008 /* Load/Store Breakpoint Intrpt Enab */
#define DER_IBRKE 0x00000004 /* Instruction Breakpoint Intrpt Enab */
#define DER_EBRKE 0x00000002 /* External Breakpoint Interrupt Enab */
#define DER_DPIE 0x00000001 /* Development Port non-maskable req enab */
#define DER_BDM_HANDLES_EVERYTHING 0xFFE7400F
#define TBRL 268 /* TimeBase Register Read Low (lsw) */
#define TBRU 269 /* TimeBase Register Read Upper (msw) */
#define TBWL 284 /* TimeBase Register Write Low (lsw) */
#define TBWU 285 /* TimeBase Register Write Upper (msw) */
#define IMMR_ 638 /* Internal Memory Map register use getIMMR() */
/* summary of all the valid DER bits */
#define DER_ALL ( \
DER_RSTE + /* Reset Interrupt Enable */ \
DER_CHSTPE + /* Check Stop Enable */ \
DER_MCIE + /* Machine Check Interrupt Enable */ \
DER_EXTIE + /* External Interrupt Enable */ \
DER_ALIE + /* Alignment Interrupt Enable */ \
DER_PRIE + /* Program Interrupt Enable */ \
DER_FPUVIE + /* Floating Point Unavail Int Enab */ \
DER_DECIE + /* Decrementer Interrupt Enable */ \
DER_SYSIE + /* System Call Interrupt Enable */ \
DER_TRE + /* Trace Interrupt Enable */ \
DER_SEIE + /* Software Emulation Intrpt Enab */ \
DER_ITLBMSE + /* Impl-Spec Instr TLB Miss Intrpt Enab */ \
DER_ITLBERE + /* Impl-Spec Instr TLB Error Enab */ \
DER_DTLBMSE + /* Impl-Spec Data TLB Miss Enab */ \
DER_DTLBERE + /* Impl-Spec Data TLB Error Enab */ \
DER_LBRKE + /* Load/Store Breakpoint Intrpt Enab */ \
DER_IBRKE + /* Instruction Breakpoint Intrpt Enab */ \
DER_EBRKE + /* External Breakpoint Interrupt Enab */ \
DER_DPIE /* Devel Port non-maskable req enab */ \
)
/* define the DER bits that are used */
#define DER_USED (DER_ALL \
- DER_DECIE \
- DER_EXTIE \
- DER_ITLBMSE \
- DER_ITLBERE \
- DER_DTLBMSE \
- DER_DTLBERE \
)
/*---------------------------------------------------------------------- */
/* MPC8xx INTERRUPT VECTOR DEFINITIONS */
/*---------------------------------------------------------------------- */
/*----------------------------------------------------------------- */
/* Number of Instructions in Vector Table for particular Interrupt */
/*----------------------------------------------------------------- */
#define VECTOR_BLOCK_LEN 0x100
/*------------------------------------ */
/* SIU Vector Interrupt Code: */
/*------------------------------------ */
#define IC_IRQ_0 0x00
#define IC_LEVEL_0 0x04
#define IC_IRQ_1 0x08
#define IC_LEVEL_1 0x0c
#define IC_IRQ_2 0x10
#define IC_LEVEL_2 0x14
#define IC_IRQ_3 0x18
#define IC_LEVEL_3 0x1c
#define IC_IRQ_4 0x20
#define IC_LEVEL_4 0x24
#define IC_IRQ_5 0x28
#define IC_LEVEL_5 0x2c
#define IC_IRQ_6 0x30
#define IC_LEVEL_6 0x34
#define IC_IRQ_7 0x38
#define IC_LEVEL_7 0x3c
/* if CPM_INTERRUPT_LEVEL is changed, then CPM_INTERRUPT_CODE MUST be changed */
#define CPM_INTERRUPT_LEVEL 4 /* integer between 0 and 7 inclusive */
#define CPM_INTERRUPT_CODE IC_LEVEL_4
/* PCMCIA INTERRUPT_LEVELS */
#define PCMCIA_MGMT_INTERRUPT_LEVEL 3 /* integer between 0 and 7 inclusive */
#define PCMCIA_MGMT_INTERRUPT_CODE IC_LEVEL_3
#define PCMCIA_MGMT_INTERRUPT_MASK SIMASK_LVM3
#define PCMCIA_IRQ_INTERRUPT_LEVEL 2 /* integer between 0 and 7 inclusive */
#define PCMCIA_IRQ_INTERRUPT_CODE IC_LEVEL_2
#define PCMCIA_IRQ_INTERRUPT_MASK SIMASK_LVM2
#define BASE_EVT 0x0 /* Base Address of Exception Vector Table */
#define EXT_INT_VECTOR ((BASE_EVT) + 0x500) /* Base address of external interrupt code */
#define DEC_INT_VECTOR ((BASE_EVT) + 0x900) /* Base address of decrementer interrupt code */
#define NEXT_VECTOR (EXT_INT_VECTOR + 0x100)
/* Interrupt Request Levels */
#define IRL0 0
#define IRL1 1
#define IRL2 2
#define IRL3 3
#define IRL4 4
#define IRL5 5
#define IRL6 6
#define IRL7 7
/* Interrupt Request Level Bitmap */
#define IRL0_bits 0x80
#define IRL1_bits 0x40
#define IRL2_bits 0x20
#define IRL3_bits 0x10
#define IRL4_bits 0x08
#define IRL5_bits 0x04
#define IRL6_bits 0x02
#define IRL7_bits 0x01
/**** Memory-mapped registers *** */
/* This section was added for initialization that has to happen */
/* at startup in assembly */
/* To address registers in c use IMMR (example: IMMR->simt_tbscr) */
/* IMM is mapped differently for different boards */
/**** Board-Specific Definitions *** */
#if (defined(CYGMA860)) /* CYGNUS ON MBX */
#define IMMBASE 0xFF000000 /* Internal register Base address */
#define IMMR_UDATA_BD 0xFF002900 /* Internal Buffer Descriptor base address */
#define IMMR_SMC1_PRAM 0xFF003E80 /* Internal Buffer Descriptor base address */
#define IMMR_SMC2_PRAM 0xFF003F80 /* Internal Buffer Descriptor base address */
#elif (ADS860 || FADS860) /* ADS860 board */
#define IMMBASE 0xFF000000 /* Internal register Base address */
#define IMMR_UDATA_BD 0xFF002800 /* Internal Buffer Descriptor base address */
#define IMMR_SMC1_PRAM 0xFF003E80 /* Internal Buffer Descriptor base address */
#define IMMR_SMC2_PRAM 0xFF003F80 /* Internal Buffer Descriptor base address */
#elif (MPC860) /* MPC860 */
#define IMMBASE 0xFA200000 /* Internal register Base address */
#define IMMR_UDATA_BD 0xFA202800 /* Internal Buffer Descriptor base address */
#define IMMR_SMC1_PRAM 0xFA203E80 /* Internal Buffer Descriptor base address */
#define IMMR_SMC2_PRAM 0xFA203F80 /* Internal Buffer Descriptor base address */
#else
#error: Please define a board type
#endif
/* USE getIMMR() INSTEAD of IMMBASE */
#define TBSCR_ (IMMBASE+0x200) /* Time Base Status & Cntr Reg (16 bits) */
#define TBSCR_TB_IRQ (IRL_TB<<8) /* intr level for timebase */
/* Interrupt Request Level Assignments */
#define IRL_TB IRL4_bits /* IRL for TimeBase Activities */
#define SCCR (IMMBASE+0x280) /* System Clock Control Register */
#define SCCR_COM 0x60000000 /* Clock Output Mode */
#define SCCR_COM_OEF 0x00000000 /* Output Enab Full strength */
#define SCCR_COM_OEH 0x20000000 /* Output Enab Half strength */
#define SCCR_COM_OD 0x60000000 /* Output Disabled */
#define SCCR_TBS 0x02000000 /* TimeBase Source */
#define SCCR_TBS_OSC_DIV_4_16 0x00000000 /* source = osc clk div 4 or 16 */
#define SCCR_TBS_SYS_DIV_16 0x02000000 /* source = sys clk div by 16 */
#define SCCR_RTDIV 0x01000000 /* RTC clk divide */
#define SCCR_RTDIV_DIV_4 0x00000000 /* RTC and PIT clock div by 4 */
#define SCCR_RTDIV_DIV_512 0x01000000 /* RTC and PIT clock div by 512 */
#define SCCR_RTSEL 0x00800000 /* RTC circuit input source select */
#define SCCR_RTSEL_OSCM 0x00000000 /* source = OSCM clock */
#define SCCR_RTSEL_EXTCLK 0x00800000 /* source = EXTCLK clock */
#define SCCR_CRQEN 0x00400000 /* CPM Request Enable */
#define SCCR_CRQEN_LOW 0x00000000 /* remains low freq even when not idle */
#define SCCR_CRQEN_HIGH 0x00400000 /* kicks into high freq */
#define SCCR_PRQEN 0x00200000 /* Power management Req Enab */
#define SCCR_PRQEN_LOW 0x00000000 /* remains low freq */
#define SCCR_PRQEN_HIGH 0x00200000 /* kicks into high */
#define SCCR_EBDF 0x00060000 /* External Bus Div factor */
#define SCCR_EBDF_GCLK2_DIV_1 0x00000000 /* GCLK2 div by 1 */
#define SCCR_EBDF_GCLK2_DIV_2 0x00020000 /* GCLK2 div by 2 */
#define SCCR_DFSYNC 0x00006000 /* Div Factor for SyncCLK */
#define SCCR_DFSYNC_1 0x00000000 /* div by 1 */
#define SCCR_DFSYNC_4 0x00002000 /* div by 4 */
#define SCCR_DFSYNC_16 0x00004000 /* div by 16 */
#define SCCR_DFSYNC_64 0x00006000 /* div by 64 */
#define SCCR_DFBRG 0x00001800 /* Div Factor for BRGCLK */
#define SCCR_DFBRG_1 0x00000000 /* div by 1 */
#define SCCR_DFBRG_4 0x00000800 /* div by 4 */
#define SCCR_DFBRG_16 0x00001000 /* div by 16 */
#define SCCR_DFBRG_64 0x00001800 /* div by 64 */
#define SCCR_DFNL 0x00000700 /* Div Factor Lowest Freq */
#define SCCR_DFNL_2 0x00000000 /* div by 2 */
#define SCCR_DFNL_4 0x00000100 /* div by 4 */
#define SCCR_DFNL_8 0x00000200 /* div by 8 */
#define SCCR_DFNL_16 0x00000300 /* div by 16 */
#define SCCR_DFNL_32 0x00000400 /* div by 32 */
#define SCCR_DFNL_64 0x00000500 /* div by 64 */
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