0modelsim_work.mgf

由altera提供的原码

P devclrn _in wire
V devclrn - - - -
P devpor _in wire
V devpor - - - -
X stratix_lvds_tx_parallel_register
V 000056 12 376 1071732054817 stratix_lvds_tx_out_block
E stratix_lvds_tx_out_block VERILOG 
L VL;
U VL.VERILOG_LOGIC;
G bypass_serializer string = "false"
G invert_clock string = "false"
G use_falling_clock_edge string = "false"
P clk _in wire
V clk - - - -
P datain _in wire
V datain - - - -
P dataout _out wire
V dataout - - - -
P devclrn _in wire
V devclrn - - - -
P devpor _in wire
V devpor - - - -
X stratix_lvds_tx_out_block
V 000055 12 446 1071732054822 stratix_lvds_transmitter
E stratix_lvds_transmitter VERILOG 
L VL;
U VL.VERILOG_LOGIC;
G channel_width integer = 4
G bypass_serializer string = "false"
G invert_clock string = "false"
G use_falling_clock_edge string = "false"
P clk0 _in wire
V clk0 - - - -
P enable0 _in wire
V enable0 - - - -
P datain _in wire[9:0]
V datain - - - -
P dataout _out wire
V dataout - - - -
P devclrn _in wire
V devclrn - - - -
P devpor _in wire
V devpor - - - -
X stratix_lvds_transmitter
V 000064 12 354 1071732054826 stratix_lvds_rx_parallel_register
E stratix_lvds_rx_parallel_register VERILOG 
L VL;
U VL.VERILOG_LOGIC;
G channel_width integer = 4
P clk _in wire
V clk - - - -
P enable _in wire
V enable - - - -
P datain _in wire[9:0]
V datain - - - -
P dataout _out wire[9:0]
V dataout - - - -
P devclrn _in wire
V devclrn - - - -
P devpor _in wire
V devpor - - - -
X stratix_lvds_rx_parallel_register
V 000052 12 397 1071732054831 stratix_lvds_receiver
E stratix_lvds_receiver VERILOG 
L VL;
U VL.VERILOG_LOGIC;
G channel_width integer = 4
G use_enable1 string = "false"
P clk0 _in wire
V clk0 - - - -
P enable0 _in wire
V enable0 - - - -
P enable1 _in wire
V enable1 - - - -
P datain _in wire
V datain - - - -
P dataout _out wire[9:0]
V dataout - - - -
P devclrn _in wire
V devclrn - - - -
P devpor _in wire
V devpor - - - -
X stratix_lvds_receiver
V 000037 12 294 1071732054835 m_cntr
E m_cntr VERILOG 
L VL;
U VL.VERILOG_LOGIC;
P clk _in wire
V clk - - - -
P reset _in wire
V reset - - - -
P cout _out wire
V cout - - - -
P initial_value _in wire[31:0]
V initial_value - - - -
P modulus _in wire[31:0]
V modulus - - - -
P time_delay _in wire[31:0]
V time_delay - - - -
X m_cntr
V 000037 12 294 1071732054839 n_cntr
E n_cntr VERILOG 
L VL;
U VL.VERILOG_LOGIC;
P clk _in wire
V clk - - - -
P reset _in wire
V reset - - - -
P cout _out wire
V cout - - - -
P initial_value _in wire[31:0]
V initial_value - - - -
P modulus _in wire[31:0]
V modulus - - - -
P time_delay _in wire[31:0]
V time_delay - - - -
X n_cntr
V 000041 12 409 1071732054845 scale_cntr
E scale_cntr VERILOG 
L VL;
U VL.VERILOG_LOGIC;
P clk _in wire
V clk - - - -
P reset _in wire
V reset - - - -
P cout _out wire
V cout - - - -
P high _in wire[31:0]
V high - - - -
P low _in wire[31:0]
V low - - - -
P initial_value _in wire[31:0]
V initial_value - - - -
P mode _in wire[48:1]
V mode - - - -
P time_delay _in wire[31:0]
V time_delay - - - -
P ph_tap _in wire[31:0]
V ph_tap - - - -
X scale_cntr
V 000038 12 223 1071732054849 pll_reg
E pll_reg VERILOG 
L VL;
U VL.VERILOG_LOGIC;
P q _out reg
V q - - - -
P clk _in wire
V clk - - - -
P ena _in tri1
V ena - - - -
P d _in wire
V d - - - -
P clrn _in tri1
V clrn - - - -
P prn _in tri1
V prn - - - -
X pll_reg
V 000043 12 8779 1071732054855 stratix_pll
E stratix_pll VERILOG 
L VL;
U VL.VERILOG_LOGIC;
G operation_mode string = "normal"
G qualify_conf_done string = "off"
G compensate_clock string = "clk0"
G pll_type string = "auto"
G scan_chain string = "long"
G clk0_multiply_by integer = 1
G clk0_divide_by integer = 1
G clk0_phase_shift integer = 0
G clk0_time_delay integer = 0
G clk0_duty_cycle integer = 50
G clk1_multiply_by integer = 1
G clk1_divide_by integer = 1
G clk1_phase_shift integer = 0
G clk1_time_delay integer = 0
G clk1_duty_cycle integer = 50
G clk2_multiply_by integer = 1
G clk2_divide_by integer = 1
G clk2_phase_shift integer = 0
G clk2_time_delay integer = 0
G clk2_duty_cycle integer = 50
G clk3_multiply_by integer = 1
G clk3_divide_by integer = 1
G clk3_phase_shift integer = 0
G clk3_time_delay integer = 0
G clk3_duty_cycle integer = 50
G clk4_multiply_by integer = 1
G clk4_divide_by integer = 1
G clk4_phase_shift integer = 0
G clk4_time_delay integer = 0
G clk4_duty_cycle integer = 50
G clk5_multiply_by integer = 1
G clk5_divide_by integer = 1
G clk5_phase_shift integer = 0
G clk5_time_delay integer = 0
G clk5_duty_cycle integer = 50
G extclk0_multiply_by integer = 1
G extclk0_divide_by integer = 1
G extclk0_phase_shift integer = 0
G extclk0_time_delay integer = 0
G extclk0_duty_cycle integer = 50
G extclk1_multiply_by integer = 1
G extclk1_divide_by integer = 1
G extclk1_phase_shift integer = 0
G extclk1_time_delay integer = 0
G extclk1_duty_cycle integer = 50
G extclk2_multiply_by integer = 1
G extclk2_divide_by integer = 1
G extclk2_phase_shift integer = 0
G extclk2_time_delay integer = 0
G extclk2_duty_cycle integer = 50
G extclk3_multiply_by integer = 1
G extclk3_divide_by integer = 1
G extclk3_phase_shift integer = 0
G extclk3_time_delay integer = 0
G extclk3_duty_cycle integer = 50
G primary_clock string = "inclk0"
G inclk0_input_frequency integer = 10000
G inclk1_input_frequency integer = 10000
G gate_lock_signal string = "no"
G gate_lock_counter integer = 1
G valid_lock_multiplier integer = 5
G invalid_lock_multiplier integer = 5
G switch_over_on_lossclk string = "off"
G switch_over_on_gated_lock string = "off"
G switch_over_counter integer = 1
G enable_switch_over_counter string = "off"
G feedback_source string = "e0"
G bandwidth integer = 0
G bandwidth_type string = "auto"
G down_spread string = "0.0"
G spread_frequency integer = 0
G common_rx_tx string = "off"
G rx_outclock_resource string = "auto"
G use_vco_bypass string = "false"
G use_dc_coupling string = "false"
G pfd_min integer = 0
G pfd_max integer = 0
G vco_min integer = 0
G vco_max integer = 0
G vco_center integer = 0
G m_initial integer = 1
G m integer = 1
G n integer = 1
G m2 integer = 1
G n2 integer = 1
G ss integer = 0
G l0_high integer = 1
G l0_low integer = 1
G l0_initial integer = 1
G l0_mode string = "bypass"
G l0_ph integer = 0
G l0_time_delay integer = 0
G l1_high integer = 1
G l1_low integer = 1
G l1_initial integer = 1
G l1_mode string = "bypass"
G l1_ph integer = 0
G l1_time_delay integer = 0
G g0_high integer = 1
G g0_low integer = 1
G g0_initial integer = 1
G g0_mode string = "bypass"
G g0_ph integer = 0
G g0_time_delay integer = 0
G g1_high integer = 1
G g1_low integer = 1
G g1_initial integer = 1
G g1_mode string = "bypass"
G g1_ph integer = 0
G g1_time_delay integer = 0
G g2_high integer = 1
G g2_low integer = 1
G g2_initial integer = 1
G g2_mode string = "bypass"
G g2_ph integer = 0
G g2_time_delay integer = 0
G g3_high integer = 1
G g3_low integer = 1
G g3_initial integer = 1
G g3_mode string = "bypass"
G g3_ph integer = 0
G g3_time_delay integer = 0
G e0_high integer = 1
G e0_low integer = 1
G e0_initial integer = 1
G e0_mode string = "bypass"
G e0_ph integer = 0
G e0_time_delay integer = 0
G e1_high integer = 1
G e1_low integer = 1
G e1_initial integer = 1
G e1_mode string = "bypass"
G e1_ph integer = 0
G e1_time_delay integer = 0
G e2_high integer = 1
G e2_low integer = 1
G e2_initial integer = 1
G e2_mode string = "bypass"
G e2_ph integer = 0
G e2_time_delay integer = 0
G e3_high integer = 1
G e3_low integer = 1
G e3_initial integer = 1
G e3_mode string = "bypass"
G e3_ph integer = 0
G e3_time_delay integer = 0
G m_ph integer = 0
G m_time_delay integer = 0
G n_time_delay integer = 0
G extclk0_counter string = "e0"
G extclk1_counter string = "e1"
G extclk2_counter string = "e2"
G extclk3_counter string = "e3"
G clk0_counter string = "g0"
G clk1_counter string = "g1"
G clk2_counter string = "g2"
G clk3_counter string = "g3"
G clk4_counter string = "l0"
G clk5_counter string = "l1"
G enable0_counter string = "l0"
G enable1_counter string = "l0"
G charge_pump_current integer = 0
G loop_filter_r string = "1.0"
G loop_filter_c integer = 1
G pll_compensation_delay integer = 0
G simulation_type string = "timing"
G source_is_pll string = "off"
G clk0_phase_shift_num integer = 0
G clk1_phase_shift_num integer = 0
G clk2_phase_shift_num integer = 0
G skip_vco string = "off"
G EGPP_SCAN_CHAIN integer = 289
G GPP_SCAN_CHAIN integer = 193
G TRST integer = 5000
G TRSTCLK integer = 5000
P inclk _in wire[1:0]
V inclk - - - -
P fbin _in wire
V fbin - - - -
P ena _in wire
V ena - - - -
P clkswitch _in wire
V clkswitch - - - -
P areset _in wire
V areset - - - -
P pfdena _in wire
V pfdena - - - -
P clkena _in wire[5:0]
V clkena - - - -
P extclkena _in wire[3:0]
V extclkena - - - -
P scanclk _in wire
V scanclk - - - -
P scanaclr _in wire
V scanaclr - - - -
P scandata _in wire
V scandata - - - -
P clk _out wire[5:0]
V clk - - - -
P extclk _out wire[3:0]
V extclk - - - -
P clkbad _out wire[1:0]
V clkbad - - - -
P activeclock _out wire
V activeclock - - - -
P locked _out wire
V locked - - - -
P clkloss _out wire
V clkloss - - - -
P scandataout _out wire
V scandataout - - - -
P comparator _in wire
V comparator - - - -
P enable0 _out wire
V enable0 - - - -
P enable1 _out wire
V enable1 - - - -
IB
ISB abs  integer[31:0]
ISP value _in integer[31:0]
ISE abs
ISB slowest_clk  integer[31:0]
ISP L0 _in integer[31:0]
ISP L1 _in integer[31:0]
ISP G0 _in integer[31:0]
ISP G1 _in integer[31:0]
ISP G2 _in integer[31:0]
ISP G3 _in integer[31:0]
ISP E0 _in integer[31:0]
ISP E1 _in integer[31:0]
ISP E2 _in integer[31:0]
ISP E3 _in integer[31:0]
ISP scan_chain _in reg[40:1]
ISP refclk _in integer[31:0]
ISP m_mod _in reg[31:0]
ISE slowest_clk
ISB gcd  integer[31:0]
ISP X _in integer[31:0]
ISP Y _in integer[31:0]
ISE gcd
ISB lcm  integer[31:0]
ISP A1 _in integer[31:0]
ISP A2 _in integer[31:0]
ISP A3 _in integer[31:0]
ISP A4 _in integer[31:0]
ISP A5 _in integer[31:0]
ISP A6 _in integer[31:0]
ISP A7 _in integer[31:0]
ISP A8 _in integer[31:0]
ISP A9 _in integer[31:0]
ISP A10 _in integer[31:0]
ISP P _in integer[31:0]
ISE lcm
ISB output_counter_value  integer[31:0]
ISP clk_divide _in integer[31:0]
ISP clk_mult _in integer[31:0]
ISP M _in integer[31:0]
ISP N _in integer[31:0]
ISE output_counter_value
ISB counter_mode  reg[48:1]
ISP duty_cycle _in integer[31:0]
ISP output_counter_value _in integer[31:0]
ISE counter_mode
ISB counter_high  integer[31:0]
ISP output_counter_value _in integer[31:0]
ISP duty_cycle _in integer[31:0]
ISE counter_high
ISB counter_low  integer[31:0]
ISP output_counter_value _in integer[31:0]
ISP duty_cycle _in integer[31:0]
ISE counter_low
ISB mintimedelay  integer[31:0]
ISP t1 _in integer[31:0]
ISP t2 _in integer[31:0]
ISP t3 _in integer[31:0]
ISP t4 _in integer[31:0]
ISP t5 _in integer[31:0]
ISP t6 _in integer[31:0]
ISP t7 _in integer[31:0]
ISP t8 _in integer[31:0]
ISP t9 _in integer[31:0]
ISP t10 _in integer[31:0]
ISE mintimedelay
ISB maxnegabs  integer[31:0]
ISP t1 _in integer[31:0]
ISP t2 _in integer[31:0]
ISP t3 _in integer[31:0]
ISP t4 _in integer[31:0]
ISP t5 _in integer[31:0]
ISP t6 _in integer[31:0]
ISP t7 _in integer[31:0]
ISP t8 _in integer[31:0]
ISP t9 _in integer[31:0]
ISP t10 _in integer[31:0]
ISE maxnegabs
ISB ph_adjust  integer[31:0]
ISP tap_phase _in integer[31:0]
ISP ph_base _in integer[31:0]
ISE ph_adjust
ISB counter_time_delay  integer[31:0]
ISP clk_time_delay _in integer[31:0]
ISP m_time_delay _in integer[31:0]
ISP n_time_delay _in integer[31:0]
ISE counter_time_delay
ISB counter_initial  integer[31:0]
ISP tap_phase _in integer[31:0]
ISP m _in integer[31:0]
ISP n _in integer[31:0]
ISE counter_initial
ISB counter_ph  integer[31:0]
ISP tap_phase _in integer[31:0]
ISP m _in integer[31:0]
ISP n _in integer[31:0]
ISE counter_ph
ISB translate_string  reg[48:1]
ISP mode _in reg
ISE translate_string
ISB str2int  integer[31:0]
ISP s _in reg[128:1]
ISE str2int
ISB get_int_phase_shift  integer[31:0]
ISP s _in reg[128:1]
ISP i_phase_shift _in integer[31:0]
ISE get_int_phase_shift
ISB get_phase_degree  integer[31:0]
ISP phase_shift _in integer[31:0]
ISE get_phase_degree
ISB alpha_tolower  reg[144:1]
ISP given_string _in reg[144:1]
ISE alpha_tolower
IE
X stratix_pll
V 000042 12 260 1071732054863 stratix_dll
E stratix_dll VERILOG 
L VL;
U VL.VERILOG_LOGIC;
G input_frequency integer = 10000
G phase_shift integer = 0
G sim_valid_lock integer = 1
G sim_invalid_lock integer = 5
P clk _in wire
V clk - - - -
P delayctrlout _out wire
V delayctrlout - - - -
X stratix_dll
V 000043 12 617 1071732054867 stratix_jtag
E stratix_jtag VERILOG 
L VL;
U VL.VERILOG_LOGIC;
P tms _in wire
V tms - - - -
P tck _in wire
V tck - - - -
P tdi _in wire
V tdi - - - -
P ntrst _in wire
V ntrst - - - -
P tdoutap _in wire
V tdoutap - - - -
P tdouser _in wire
V tdouser - - - -
P tdo _out wire
V tdo - - - -
P tmsutap _out wire
V tmsutap - - - -
P tckutap _out wire
V tckutap - - - -
P tdiutap _out wire
V tdiutap - - - -
P shiftuser _out wire
V shiftuser - - - -
P clkdruser _out wire
V clkdruser - - - -
P updateuser _out wire
V updateuser - - - -
P runidleuser _out wire
V runidleuser - - - -
P usr1user _out wire
V usr1user - - - -
X stratix_jtag
V 000047 12 283 1071732054875 stratix_crcblock
E stratix_crcblock VERILOG 
L VL;
U VL.VERILOG_LOGIC;
G oscillator_divider integer = 1
P clk _in wire
V clk - - - -
P shiftnld _in wire
V shiftnld - - - -
P ldsrc _in wire
V ldsrc - - - -
P crcerror _out wire
V crcerror - - - -
P regout _out wire
V regout - - - -
X stratix_crcblock
V 000046 12 544 1071732054882 stratix_rublock
E stratix_rublock VERILOG 
L VL;
U VL.VERILOG_LOGIC;
G sim_in