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Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file D:/湖南合力公司/rs232-lan/rs232lan/rs232lan_vhl.vhdl in Library work.Entity <rs232lan_vhl> (Architecture <Behavioral>) compiled.=========================================================================* HDL Analysis *=========================================================================Analyzing Entity <rs232lan_vhl> (Architecture <Behavioral>).Entity <rs232lan_vhl> analyzed. Unit <rs232lan_vhl> generated.=========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <rs232lan_vhl>. Related source file is D:/湖南合力公司/rs232-lan/rs232lan/rs232lan_vhl.vhdl. Found 1-bit tristate buffer for signal <irq12>. Found 1-bit tristate buffer for signal <irq15>. Summary: inferred 2 Tristate(s).Unit <rs232lan_vhl> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# Tristates : 2 1-bit tristate buffer : 2==================================================================================================================================================* Low Level Synthesis *=========================================================================Optimizing unit <rs232lan_vhl> ...Completed process "Synthesize".
Started process "Translate".Extracting independent architecture files...Release 6.2i - ngdbuild G.28Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.Command Line: ngdbuild -dd _ngo -i -p xc9500 rs232lan_vhl.ngc rs232lan_vhl.ngd Reading NGO file "D:/湖南合力公司/rs232-lan/rs232lan/rs232lan_vhl.ngc" ...Reading component libraries for design expansion...Checking timing specifications ...Checking expanded design ...NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0Total memory usage is 38048 kilobytesWriting NGD file "rs232lan_vhl.ngd" ...Writing NGDBUILD log file "rs232lan_vhl.bld"...NGDBUILD done.Completed process "Translate".
Started process "Fit".Release 6.2i - CPLD Optimizer/Partitioner G.28Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.Considering device XC9536-10-VQ44.Flattening design..Timing optimizationTiming driven global resource optimizationGeneral global resource optimization........Re-checking device resources ...Mapping a total of 11 equations into 2 function blocks..........字符转换错误：“Unconvertible UTF-8 character beginning with 0xba”（行号可能太小）。line number 1Entity nullFailed to open: rs232lan_vhl_build.xmlDesign rs232lan_vhl has been optimized and fit into device XC9536-10-VQ44.Completed process "Fit".
Started process "Generate Programming File".Release 6.2i - Programming File Generator G.28Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.Completed process "Generate Programming File".
Started process "Generate Timing".Release 6.2i - Timing Report Generator G.28Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.Path tracing .....The number of paths traced: 54.The number of paths traced: 109.Generating TA GUI report ...Generating detailed paths report ...Generating asynchronous checking report ...d:\湖南合力公司\rs232-lan\rs232lan/rs232lan_vhl_html/tim/timing_report.htm hasbeen created.d:\湖南合力公司\rs232-lan\rs232lan/rs232lan_vhl_html/tim/timing_report.htm hasbeen created.Completed process "Generate Timing".
Started process "Generate HTML report".Release 6.2i - CPLD HTML Report Processor G.28Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.字符转换错误：“Unconvertible UTF-8 character beginning with 0xba”（行号可能太小）。line number 1Entity nullFailed to open: rs232lan_vhl_build.xmlERROR:Cpld:1137 - Child process failed -mode 1
Project Navigator Auto-Make Log File-------------------------------------
Started process "Translate".Release 6.2i - ngdbuild G.28Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.Command Line: ngdbuild -dd _ngo -uc RS232LAN.ucf -p xc9500 rs232lan_vhl.ngcrs232lan_vhl.ngd Reading NGO file "D:/湖南合力公司/rs232-lan/rs232lan/rs232lan_vhl.ngc" ...Reading component libraries for design expansion...Annotating constraints to design from file "RS232LAN.ucf" ...Checking timing specifications ...Checking expanded design ...NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0Total memory usage is 40096 kilobytesWriting NGD file "rs232lan_vhl.ngd" ...Writing NGDBUILD log file "rs232lan_vhl.bld"...NGDBUILD done.Completed process "Translate".
Project Navigator Auto-Make Log File-------------------------------------
Started process "Fit".Release 6.2i - CPLD Optimizer/Partitioner G.28Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.Considering device XC9536-10-VQ44.Flattening design..Timing optimizationTiming driven global resource optimizationGeneral global resource optimization........Re-checking device resources ...Mapping a total of 11 equations into 2 function blocks字符转换错误：“Unconvertible UTF-8 character beginning with 0xba”（行号可能太小）。line number 1Entity nullFailed to open: rs232lan_vhl_build.xmlDesign rs232lan_vhl has been optimized and fit into device XC9536-10-VQ44.Completed process "Fit".
Started process "Generate Programming File".Release 6.2i - Programming File Generator G.28Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.Completed process "Generate Programming File".
Started process "Generate Timing".Release 6.2i - Timing Report Generator G.28Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.Path tracing .....The number of paths traced: 54.The number of paths traced: 109.Generating TA GUI report ...Generating detailed paths report ...Generating asynchronous checking report ...d:\湖南合力公司\rs232-lan\rs232lan/rs232lan_vhl_html/tim/timing_report.htm hasbeen created.d:\湖南合力公司\rs232-lan\rs232lan/rs232lan_vhl_html/tim/timing_report.htm hasbeen created.Completed process "Generate Timing".
Started process "Generate HTML report".Release 6.2i - CPLD HTML Report Processor G.28Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.字符转换错误：“Unconvertible UTF-8 character beginning with 0xba”（行号可能太小）。line number 1Entity nullFailed to open: rs232lan_vhl_build.xmlERROR:Cpld:1137 - Child process failed -mode 1
Project Navigator Auto-Make Log File-------------------------------------
Started process "Generate Programming File".Release 6.2i - Programming File Generator G.28Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.Completed process "Generate Programming File".
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