📄 rs232lan_vhl.rpt
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cpldfit: version G.28 Xilinx Inc.
Fitter Report
Design Name: rs232lan_vhl Date: 1-12-2007, 10:00AM
Device Used: XC9536-10-VQ44
Fitting Status: Successful
**************************** Resource Summary ****************************
Macrocells Product Terms Registers Pins Function Block
Used Used Used Used Inputs Used
11 /36 ( 31%) 14 /180 ( 8%) 0 /36 ( 0%) 34 /34 (100%) 23 /72 ( 32%)
PIN RESOURCES:
Signal Type Required Mapped | Pin Type Used Remaining
------------------------------------|---------------------------------------
Input : 23 23 | I/O : 28 0
Output : 11 11 | GCK/IO : 3 0
Bidirectional : 0 0 | GTS/IO : 2 0
GCK : 0 0 | GSR/IO : 1 0
GTS : 0 0 |
GSR : 0 0 |
---- ----
Total 34 34
MACROCELL RESOURCES:
Total Macrocells Available 36
Registered Macrocells 0
Non-registered Macrocell driving I/O 11
GLOBAL RESOURCES:
Global clock net(s) unused.
Global output enable net(s) unused.
Global set/reset net(s) unused.
POWER DATA:
There are 11 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
There are a total of 11 macrocells used (MC).
End of Resource Summary
*************** Summary of Required Resources ******************
** LOGIC **
Signal Total Signals Loc Pwr Slew Pin Pin Pin Reg Init
Name Pt Used Mode Rate # Type Use State
cs1 2 10 FB1_6 STD FAST 2 I/O O
cs2 2 10 FB1_5 STD FAST 44 GCK/I/O O
cs3 2 10 FB1_4 STD FAST 42 I/O O
cs4 2 10 FB1_7 STD FAST 1 GCK/I/O O
doc_cs 2 10 FB1_16 STD FAST 16 I/O O
irq10 1 1 FB1_12 STD FAST 8 I/O O
irq11 1 1 FB1_13 STD FAST 12 I/O O
irq12 0 0 FB1_14 STD FAST 13 I/O O
irq15 0 0 FB1_15 STD FAST 14 I/O O
irq5 1 1 FB1_10 STD FAST 6 I/O O
irq7 1 1 FB1_11 STD FAST 7 I/O O
** INPUTS **
Signal Loc Pin Pin Pin
Name # Type Use
aen FB1_17 18 I/O I
ior FB2_14 22 I/O I
iow FB2_15 21 I/O I
irqcom1 FB1_9 5 I/O I
irqcom2 FB1_3 43 GCK/I/O I
irqcom3 FB1_2 41 I/O I
irqcom4 FB1_8 3 I/O I
sa13 FB2_7 32 I/O I
sa14 FB2_8 31 I/O I
sa15 FB2_9 30 I/O I
sa16 FB2_10 29 I/O I
sa17 FB2_11 28 I/O I
sa18 FB2_12 27 I/O I
sa19 FB2_13 23 I/O I
sa3 FB1_1 40 I/O I
sa4 FB2_1 39 I/O I
sa5 FB2_2 38 I/O I
sa6 FB2_4 37 I/O I
sa7 FB2_3 36 GTS/I/O I
sa8 FB2_5 34 GTS/I/O I
sa9 FB2_6 33 GSR/I/O I
smemr FB2_16 20 I/O I
smemw FB2_17 19 I/O I
End of Resources
*********************Function Block Resource Summary***********************
Function # of FB Inputs Signals Total O/IO IO
Block Macrocells Used Used Pt Used Req Avail
FB1 11 23 23 14 11/0 17
FB2 0 0 0 0 0/0 17
---- ----- ----- -----
11 14 11/0 34
*********************************** FB1 ***********************************
Number of function block inputs used/remaining: 23/13
Number of signals used by logic mapping into function block: 23
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB1_1 40 I/O I
(unused) 0 0 0 5 FB1_2 41 I/O I
(unused) 0 0 0 5 FB1_3 43 GCK/I/O I
cs3 2 0 0 3 FB1_4 STD 42 I/O O
cs2 2 0 0 3 FB1_5 STD 44 GCK/I/O O
cs1 2 0 0 3 FB1_6 STD 2 I/O O
cs4 2 0 0 3 FB1_7 STD 1 GCK/I/O O
(unused) 0 0 0 5 FB1_8 3 I/O I
(unused) 0 0 0 5 FB1_9 5 I/O I
irq5 1 0 0 4 FB1_10 STD 6 I/O O
irq7 1 0 0 4 FB1_11 STD 7 I/O O
irq10 1 0 0 4 FB1_12 STD 8 I/O O
irq11 1 0 0 4 FB1_13 STD 12 I/O O
irq12 0 0 0 5 FB1_14 STD 13 I/O O
irq15 0 0 0 5 FB1_15 STD 14 I/O O
doc_cs 2 0 0 3 FB1_16 STD 16 I/O O
(unused) 0 0 0 5 FB1_17 18 I/O I
(unused) 0 0 0 5 FB1_18 (b)
Signals Used by Logic in Function Block
1: aen 9: sa14 17: sa5
2: ior 10: sa15 18: sa6
3: iow 11: sa16 19: sa7
4: irqcom3 12: sa17 20: sa8
5: irqcom4 13: sa18 21: sa9
6: irqcom1 14: sa19 22: smemr
7: irqcom2 15: sa3 23: smemw
8: sa13 16: sa4
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
cs3 XXX...........XXXXXXX................... 10 10
cs2 XXX...........XXXXXXX................... 10 10
cs1 XXX...........XXXXXXX................... 10 10
cs4 XXX...........XXXXXXX................... 10 10
irq5 .....X.................................. 1 1
irq7 ......X................................. 1 1
irq10 ...X.................................... 1 1
irq11 ....X................................... 1 1
irq12 ........................................ 0 0
irq15 ........................................ 0 0
doc_cs X......XXXXXXX.......XX................. 10 10
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB2 ***********************************
Number of function block inputs used/remaining: 0/36
Number of signals used by logic mapping into function block: 0
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB2_1 39 I/O I
(unused) 0 0 0 5 FB2_2 38 I/O I
(unused) 0 0 0 5 FB2_3 36 GTS/I/O I
(unused) 0 0 0 5 FB2_4 37 I/O I
(unused) 0 0 0 5 FB2_5 34 GTS/I/O I
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