📄 f24x_a.h
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;/*************************************************************************
; File name: 240x.h
;
; Description: 240x register definitions, Bit codes for BIT instruction
;************************************************************************/
; 240x CPU core registers
IMR .set 0004h ; Interrupt Mask Register
IFR .set 0006h ; Interrupt Flag register
; System configuration and interrupt registers
SCSR1 .set 7018h ; System Control & Status register. 1
SCSR2 .set 7019h ; System Control & Status register. 2
DINR .set 701Ch ; Device Identification Number register.
PIVR .set 701Eh ; Peripheral Interrupt Vector register.
PIRQR0 .set 7010h ; Peripheral Interrupt Request register 0
PIRQR1 .set 7011h ; Peripheral Interrupt Request register 1
PIRQR2 .set 7012h ; Peripheral Interrupt Request register 2
PIACKR0 .set 7014h ; Peripheral Interrupt Acknowledge register 0
PIACKR1 .set 7015h ; Peripheral Interrupt Acknowledge register 1
PIACKR2 .set 7016h ; Peripheral Interrupt Acknowledge register 2
; External interrupt configuration registers
XINT1CR .set 7070h ; External interrupt 1 control register
XINT2CR .set 7071h ; External interrupt 2 control register
; Digital I/O registers
MCRA .set 7090h ; I/O Mux Control Register A
MCRB .set 7092h ; I/O Mux Control Register B
MCRC .set 7094h ; I/O Mux Control Register C
PADATDIR .set 7098h ; I/O port A Data & Direction register
PBDATDIR .set 709Ah ; I/O port B Data & Direction register
PCDATDIR .set 709Ch ; I/O port C Data & Direction register
PDDATDIR .set 709Eh ; I/O port D Data & Direction register
PEDATDIR .set 7095h ; I/O port E Data & Direction register
PFDATDIR .set 7096h ; I/O port F Data & Direction register
; Watchdog (WD) registers
WDCNTR .set 7023h ; WD Counter register
WDKEY .set 7025h ; WD Key register
WDCR .set 7029h ; WD Control register
; ADC registers
ADCTRL1 .set 70A0h ; ADC Control register 1
ADCTRL2 .set 70A1h ; ADC Control register 2
MAXCONV .set 70A2h ; Maximum conversion channels register
CHSELSEQ1 .set 70A3h ; Channel select Sequencing control register 1
CHSELSEQ2 .set 70A4h ; Channel select Sequencing control register 2
CHSELSEQ3 .set 70A5h ; Channel select Sequencing control register 3
CHSELSEQ4 .set 70A6h ; Channel select Sequencing control register 4
AUTO_SEQ_SR .set 70A7h ; Auto–sequence status register
RESULT0 .set 70A8h ; Conversion result buffer register 0
RESULT1 .set 70A9h ; Conversion result buffer register 1
RESULT2 .set 70Aah ; Conversion result buffer register 2
RESULT3 .set 70Abh ; Conversion result buffer register 3
RESULT4 .set 70Ach ; Conversion result buffer register 4
RESULT5 .set 70Adh ; Conversion result buffer register 5
RESULT6 .set 70Aeh ; Conversion result buffer register 6
RESULT7 .set 70Afh ; Conversion result buffer register 7
RESULT8 .set 70B0h ; Conversion result buffer register 8
RESULT9 .set 70B1h ; Conversion result buffer register 9
RESULT10 .set 70B2h ; Conversion result buffer register 10
RESULT11 .set 70B3h ; Conversion result buffer register 11
RESULT12 .set 70B4h ; Conversion result buffer register 12
RESULT13 .set 70B5h ; Conversion result buffer register 13
RESULT14 .set 70B6h ; Conversion result buffer register 14
RESULT15 .set 70B7h ; Conversion result buffer register 15
CALIBRATION .set 70B8h ; Calib result, used to correct
; subsequent conversions
; SPI registers
SPICCR .set 7040h ; SPI Config Control register
SPICTL .set 7041h ; SPI Operation Control register
SPISTS .set 7042h ; SPI Status register
SPIBRR .set 7044h ; SPI Baud rate control register
SPIRXEMU .set 7046h ; SPI Emulation buffer register
SPIRXBUF .set 7047h ; SPI Serial receive buffer register
SPITXBUF .set 7048h ; SPI Serial transmit buffer register
SPIDAT .set 7049h ; SPI Serial data register
SPIPRI .set 704Fh ; SPI Priority control register
; SCI registers
SCICCR .set 7050h ; SCI Communication control register
SCICTL1 .set 7051h ; SCI Control register 1
SCIHBAUD .set 7052h ; SCI Baud Rate MS byte register
SCILBAUD .set 7053h ; SCI Baud Rate LS byte register
SCICTL2 .set 7054h ; SCI Control register 2
SCIRXST .set 7055h ; SCI Receiver Status register
SCIRXEMU .set 7056h ; SCI Emulation Data Buffer register
SCIRXBUF .set 7057h ; SCI Receiver Data buffer register
SCITXBUF .set 7059h ; SCI Transmit Data buffer register
SCIPRI .set 705Fh ; SCI Priority control register
; Event Manager A (EVA) registers
GPTCONA .set 7400h ; GP Timer control register A
T1CNT .set 7401h ; GP Timer 1 counter register
T1CMPR .set 7402h ; GP Timer 1 compare register
T1PR .set 7403h ; GP Timer 1 period register
T1CON .set 7404h ; GP Timer 1 control register
T2CNT .set 7405h ; GP Timer 2 counter register
T2CMPR .set 7406h ; GP Timer 2 compare register
T2PR .set 7407h ; GP Timer 2 period register
T2CON .set 7408h ; GP Timer 2 control register
COMCONA .set 7411h ; Compare control register A
ACTRA .set 7413h ; Full compare Action control register A
DBTCONA .set 7415h ; Dead–band timer control register A
CMPR1 .set 7417h ; Full compare unit compare register1
CMPR2 .set 7418h ; Full compare unit compare register2
CMPR3 .set 7419h ; Full compare unit compare register3
CAPCONA .set 7420h ; Capture control register A
CAPFIFOA .set 7422h ; Capture FIFO status register A
CAP1FIFO .set 7423h ; Capture Channel 1 FIFO Top
CAP2FIFO .set 7424h ; Capture Channel 2 FIFO Top
CAP3FIFO .set 7425h ; Capture Channel 3 FIFO Top
CAP1FBOT .set 7427h ; Bottom reg. of capture FIFO stack 1
CAP2FBOT .set 7428h ; Bottom reg. of capture FIFO stack 2
CAP3FBOT .set 7429h ; Bottom reg. of capture FIFO stack 3
EVAIMRA .set 742Ch ; Group A Interrupt Mask Register
EVAIMRB .set 742Dh ; Group B Interrupt Mask Register
EVAIMRC .set 742Eh ; Group C Interrupt Mask Register
EVAIFRA .set 742Fh ; Group A Interrupt Flag Register
EVAIFRB .set 7430h ; Group B Interrupt Flag Register
EVAIFRC .set 7431h ; Group C Interrupt Flag register
; Event Manager B (EVB) registers
GPTCONB .set 7500h ; GP Timer control register B
T3CNT .set 7501h ; GP Timer 3 counter register
T3CMPR .set 7502h ; GP Timer 3 compare register
T3PR .set 7503h ; GP Timer 3 period register
T3CON .set 7504h ; GP Timer 3 control register
T4CNT .set 7505h ; GP Timer 4 counter register
T4CMPR .set 7506h ; GP Timer 4 compare register
T4PR .set 7507h ; GP Timer 4 period register
T4CON .set 7508h ; GP Timer 4 control register
COMCONB .set 7511h ; Compare control register B
ACTRB .set 7513h ; Full compare Action control register B
DBTCONB .set 7515h ; Dead–band timer control register B
CMPR4 .set 7517h ; Full compare unit compare register4
CMPR5 .set 7518h ; Full compare unit compare register5
CMPR6 .set 7519h ; Full compare unit compare register6
CAPCONB .set 7520h ; Capture control register B
CAPFIFOB .set 7522h ; Capture FIFO status register B
CAP4FIFO .set 7523h ; Capture Channel 4 FIFO Top
CAP5FIFO .set 7524h ; Capture Channel 5 FIFO Top
CAP6FIFO .set 7525h ; Capture Channel 6 FIFO Top
CAP4FBOT .set 7527h ; Bottom reg. of capture FIFO stack 4
CAP5FBOT .set 7527h ; Bottom reg. of capture FIFO stack 5
CAP6FBOT .set 7527h ; Bottom reg. of capture FIFO stack 6
EVBIMRA .set 752Ch ; Group A Interrupt Mask Register
EVBIMRB .set 752Dh ; Group B Interrupt Mask Register
EVBIMRC .set 752Eh ; Group C Interrupt Mask Register
EVBIFRA .set 752Fh ; Group A Interrupt Flag Register
EVBIFRB .set 7530h ; Group B Interrupt Flag Register
EVBIFRC .set 7531h ; Group C Interrupt Flag register
; CAN registers
CANMDER .set 7100h ; CAN Mailbox Direction/Enable register
CANTCR .set 7101h ; CAN Transmission Control register
CANRCR .set 7102h ; CAN Recieve Control register
CANMCR .set 7103h ; CAN Master Control register
CANBCR2 .set 7104h ; CAN Bit Config register 2
CANBCR1 .set 7105h ; CAN Bit Config register 1
CANESR .set 7106h ; CAN Error Status register
CANGSR .set 7107h ; CAN Global Status register
CANCEC .set 7108h ; CAN Trans and Rcv Err counters
CANIFR .set 7109h ; CAN Interrupt Flag Register
CANIMR .set 710ah ; CAN Interrupt Mask Register
CANLAM0H .set 710bh ; CAN Local Acceptance Mask MBX0/1
CANLAM0L .set 710ch ; CAN Local Acceptance Mask MBX0/1
CANLAM1H .set 710dh ; CAN Local Acceptance Mask MBX2/3
CANLAM1L .set 710eh ; CAN Local Acceptance Mask MBX2/3
CANMSGID0L .set 7200h ; CAN Message ID for mailbox 0 (lower 16 bits)
CANMSGID0H .set 7201h ; CAN Message ID for mailbox 0 (upper 16 bits)
CANMSGCTRL0 .set 7202h ; CAN RTR and DLC
CANMBX0A .set 7204h ; CAN 2 of 8 bytes of Mailbox 0
CANMBX0B .set 7205h ; CAN 2 of 8 bytes of Mailbox 0
CANMBX0C .set 7206h ; CAN 2 of 8 bytes of Mailbox 0
CANMBX0D .set 7207h ; CAN 2 of 8 bytes of Mailbox 0
CANMSGID1L .set 7208h ; CAN Message ID for mailbox 1 (lower 16 bits)
CANMSGID1H .set 7209h ; CAN Message ID for mailbox 1 (upper 16 bits)
CANMSGCTRL1 .set 720Ah ; CAN RTR and DLC
CANMBX1A .set 720Ch ; CAN 2 of 8 bytes of Mailbox 1
CANMBX1B .set 720Dh ; CAN 2 of 8 bytes of Mailbox 1
CANMBX1C .set 720Eh ; CAN 2 of 8 bytes of Mailbox 1
CANMBX1D .set 720Fh ; CAN 2 of 8 bytes of Mailbox 1
CANMSGID2L .set 7210h ; CAN Message ID for mailbox 2 (lower 16 bits)
CANMSGID2H .set 7211h ; CAN Message ID for mailbox 2 (upper 16 bits)
CANMSGCTRL2 .set 7212h ; CAN RTR and DLC
CANMBX2A .set 7214h ; CAN 2 of 8 bytes of Mailbox 2
CANMBX2B .set 7215h ; CAN 2 of 8 bytes of Mailbox 2
CANMBX2C .set 7216h ; CAN 2 of 8 bytes of Mailbox 2
CANMBX2D .set 7217h ; CAN 2 of 8 bytes of Mailbox 2
CANMSGID3L .set 7218h ; CAN Message ID for mailbox 3 (lower 16 bits)
CANMSGID3H .set 7219h ; CAN Message ID for mailbox 3 (upper 16 bits)
CANMSGCTRL3 .set 721Ah ; CAN RTR and DLC
CANMBX3A .set 721Ch ; CAN 2 of 8 bytes of Mailbox 3
CANMBX3B .set 721Dh ; CAN 2 of 8 bytes of Mailbox 3
CANMBX3C .set 721Eh ; CAN 2 of 8 bytes of Mailbox 3
CANMBX3D .set 721Fh ; CAN 2 of 8 bytes of Mailbox 3
CANMSGID4L .set 7220h ; CAN Message ID for mailbox 4 (lower 16 bits)
CANMSGID4H .set 7221h ; CAN Message ID for mailbox 4 (upper 16 bits)
CANMSGCTRL4 .set 7222h ; CAN RTR and DLC
CANMBX4A .set 7224h ; CAN 2 of 8 bytes of Mailbox 4
CANMBX4B .set 7225h ; CAN 2 of 8 bytes of Mailbox 4
CANMBX4C .set 7226h ; CAN 2 of 8 bytes of Mailbox 4
CANMBX4D .set 7227h ; CAN 2 of 8 bytes of Mailbox 4
CANMSGID5L .set 7228h ; CAN Message ID for mailbox 5 (lower 16 bits)
CANMSGID5H .set 7229h ; CAN Message ID for mailbox 5 (upper 16 bits)
CANMSGCTRL5 .set 722Ah ; CAN RTR and DLC
CANMBX5A .set 722Ch ; CAN 2 of 8 bytes of Mailbox 5
CANMBX5B .set 722Dh ; CAN 2 of 8 bytes of Mailbox 5
CANMBX5C .set 722Eh ; CAN 2 of 8 bytes of Mailbox 5
CANMBX5D .set 722Fh ; CAN 2 of 8 bytes of Mailbox 5
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; I/O space mapped registers
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
WSGR .set 0FFFFh ; Wait–State Generator Control register
FCMR .set 0FF0Fh ; Flash control mode register
;––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; Bit codes for Test bit instruction (BIT) (15 Loads bit 0 into TC)
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
BIT15 .set 0000h ; Bit Code for 15
BIT14 .set 0001h ; Bit Code for 14
BIT13 .set 0002h ; Bit Code for 13
BIT12 .set 0003h ; Bit Code for 12
BIT11 .set 0004h ; Bit Code for 11
BIT10 .set 0005h ; Bit Code for 10
BIT9 .set 0006h ; Bit Code for 9
BIT8 .set 0007h ; Bit Code for 8
BIT7 .set 0008h ; Bit Code for 7
BIT6 .set 0009h ; Bit Code for 6
BIT5 .set 000Ah ; Bit Code for 5
BIT4 .set 000Bh ; Bit Code for 4
BIT3 .set 000Ch ; Bit Code for 3
BIT2 .set 000Dh ; Bit Code for 2
BIT1 .set 000Eh ; Bit Code for 1
BIT0 .set 000Fh ; Bit Code for 0⌨️ 快捷键说明
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