mc8051_top.srr

我在spartan-3e starter kit 的板上实现了mc8051

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@N: CD720 :"d:\Synplicity\fpga_862\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns
@I:: "E:\vtest\xilinx\vhdl8051\mc8051\mc8051_p.vhd"
@I:: "E:\vtest\xilinx\vhdl8051\mc8051\addsub_ovcy_.vhd"
@I:: "E:\vtest\xilinx\vhdl8051\mc8051\addsub_cy_.vhd"
@I:: "E:\vtest\xilinx\vhdl8051\mc8051\addsub_ovcy_rtl.vhd"
@I:: "E:\vtest\xilinx\vhdl8051\mc8051\addsub_cy_rtl.vhd"
@I:: "E:\vtest\xilinx\vhdl8051\mc8051\dcml_adjust_.vhd"
@I:: "E:\vtest\xilinx\vhdl8051\mc8051\control_mem_.vhd"
@I:: "E:\vtest\xilinx\vhdl8051\mc8051\control_fsm_.vhd"
@I:: "E:\vtest\xilinx\vhdl8051\mc8051\comb_mltplr_.vhd"
@I:: "E:\vtest\xilinx\vhdl8051\mc8051\comb_divider_.vhd"
@I:: "E:\vtest\xilinx\vhdl8051\mc8051\alumux_.vhd"
@I:: "E:\vtest\xilinx\vhdl8051\mc8051\alucore_.vhd"
@I:: "E:\vtest\xilinx\vhdl8051\mc8051\addsub_core_.vhd"
@I:: "E:\vtest\xilinx\vhdl8051\mc8051\dcml_adjust_rtl.vhd"
@I:: "E:\vtest\xilinx\vhdl8051\mc8051\control_mem_rtl.vhd"
@I:: "E:\vtest\xilinx\vhdl8051\mc8051\control_fsm_rtl.vhd"
@I:: "E:\vtest\xilinx\vhdl8051\mc8051\comb_mltplr_rtl.vhd"
@I:: "E:\vtest\xilinx\vhdl8051\mc8051\comb_divider_rtl.vhd"
@I:: "E:\vtest\xilinx\vhdl8051\mc8051\alumux_rtl.vhd"
@I:: "E:\vtest\xilinx\vhdl8051\mc8051\alucore_rtl.vhd"
@I:: "E:\vtest\xilinx\vhdl8051\mc8051\addsub_core_struc.vhd"
@I:: "E:\vtest\xilinx\vhdl8051\mc8051\mc8051_tmrctr_.vhd"
@I:: "E:\vtest\xilinx\vhdl8051\mc8051\mc8051_siu_.vhd"
@I:: "E:\vtest\xilinx\vhdl8051\mc8051\mc8051_control_.vhd"
@I:: "E:\vtest\xilinx\vhdl8051\mc8051\mc8051_alu_.vhd"
@I:: "E:\vtest\xilinx\vhdl8051\mc8051\mc8051_tmrctr_rtl.vhd"
@I:: "E:\vtest\xilinx\vhdl8051\mc8051\mc8051_siu_rtl.vhd"
@I:: "E:\vtest\xilinx\vhdl8051\mc8051\mc8051_control_struc.vhd"
@I:: "E:\vtest\xilinx\vhdl8051\mc8051\mc8051_alu_struc.vhd"
@I:: "E:\vtest\xilinx\vhdl8051\mc8051\mc8051_core_.vhd"
@I:: "E:\vtest\xilinx\vhdl8051\mc8051\mc8051_clockdiv.vhd"
@I:: "E:\vtest\xilinx\vhdl8051\mc8051\mc8051_core_struc.vhd"
@I:: "E:\vtest\xilinx\vhdl8051\mc8051\mc8051_top_.vhd"
VHDL syntax check successful!

Compiler output is up to date.  No re-compile necessary

@N: CD630 :"E:\vtest\xilinx\vhdl8051\mc8051\mc8051_top_.vhd":74:7:74:16|Synthesizing work.mc8051_top.struc 
@W: CD638 :"E:\vtest\xilinx\vhdl8051\mc8051\mc8051_top_.vhd":120:9:120:22|Signal s_ramx_data_in is undriven 
@N: CD630 :"E:\vtest\xilinx\vhdl8051\mc8051\mc8051_clockdiv.vhd":30:7:30:21|Synthesizing work.mc8051_clockdiv.behavioral 
Post processing for work.mc8051_clockdiv.behavioral
@N: CD630 :"E:\vtest\xilinx\vhdl8051\mc8051\mc8051_core_.vhd":75:7:75:17|Synthesizing work.mc8051_core.struc 
@W: CD638 :"E:\vtest\xilinx\vhdl8051\mc8051\mc8051_core_struc.vhd":80:9:80:15|Signal s_reset is undriven 
@W: CD638 :"E:\vtest\xilinx\vhdl8051\mc8051\mc8051_core_struc.vhd":81:9:81:13|Signal s_clk is undriven 
@N: CD630 :"E:\vtest\xilinx\vhdl8051\mc8051\mc8051_tmrctr_.vhd":71:7:71:19|Synthesizing wo