mc8051_top.prj

我在spartan-3e starter kit 的板上实现了mc8051

#
##-- Synplicity, Inc.
##-- Project file mc8051_top.prj.
##-- Generated using ISE.

#implementation: mc8051_top
impl -add "mc8051_top"

##device options
proc findmatch {spec args} {  set _Arglist [join $args " "];  set _Idx [lsearch -glob $_Arglist $spec];  if {$_Idx != -1} {  return [lindex $_Arglist $_Idx];  } else {  return $spec;  }  }
         
proc findpackage {spec} { findmatch $spec [partdata -package [part]]}
proc findgrade   {spec} { findmatch $spec [partdata -grade   [part]]}
set_option -technology SPARTAN3E
set_option -part xc3s500e
set_option -package [findpackage {fg320}]
set_option -speed_grade [findgrade {-4}]

## Libraries

## Source files
add_file -verilog {"d:/Synplicity/fpga_862/bin/../lib/xilinx/unisim.v"}
add_file {mc8051_p.vhd}
add_file {addsub_ovcy_.vhd}
add_file {addsub_cy_.vhd}
add_file {addsub_ovcy_rtl.vhd}
add_file {addsub_cy_rtl.vhd}
add_file {dcml_adjust_.vhd}
add_file {control_mem_.vhd}
add_file {control_fsm_.vhd}
add_file {comb_mltplr_.vhd}
add_file {comb_divider_.vhd}
add_file {alumux_.vhd}
add_file {alucore_.vhd}
add_file {addsub_core_.vhd}
add_file {dcml_adjust_rtl.vhd}
add_file {control_mem_rtl.vhd}
add_file {control_fsm_rtl.vhd}
add_file {comb_mltplr_rtl.vhd}
add_file {comb_divider_rtl.vhd}
add_file {alumux_rtl.vhd}
add_file {alucore_rtl.vhd}
add_file {addsub_core_struc.vhd}
add_file {mc8051_tmrctr_.vhd}
add_file {mc8051_siu_.vhd}
add_file {mc8051_control_.vhd}
add_file {mc8051_alu_.vhd}
add_file {mc8051_tmrctr_rtl.vhd}
add_file {mc8051_siu_rtl.vhd}
add_file {mc8051_control_struc.vhd}
add_file {mc8051_alu_struc.vhd}
add_file {mc8051_core_.vhd}
add_file {mc8051_clockdiv.vhd}
add_file {mc8051_rom.v}
add_file {mc8051_ram.v}
add_file {mc8051_core_struc.vhd}
add_file {mc8051_top_.vhd}

## Additional _Compile options
set_option -symbolic_fsm_compiler 1
set_option -resource_sharing 1
set_option -default_enum_encoding default
set_option -top_module mc8051_top
set_option -use_fsm_explorer 0

## Additional _Map options
set_option -frequency auto
set_option -fanout_limit 100
set_option -disable_io_insertion 0
set_option -pipe 1
set_option -modular 0
set_option -retiming 0

## Additional _Simulation options
set_option -write_verilog 0
set_option -write_vhdl 0

## Additional _PlaceAndRoute options
set_option -write_apr_constraint 1

## Additional _ImplAttr options
set_option -num_critical_paths 0
set_option -num_startend_points 0

set_option -vlog_std v2001
set_option -compiler_compatible 0

##--Set result format/file last
project -result_file {E:/vtest/xilinx/vhdl8051/mc8051/mc8051_top.edn}

##-- p_Constraint file
add_file -constraint {E:/vtest/xilinx/vhdl8051/mc8051/mc8051_top.sdc}