📄 p30f4012.inc
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; High Byte (Odd Address)
; Bit Positions defined below:
.equiv POVD3H, 0x000D
.equiv POVD3L, 0x000C
.equiv POVD2H, 0x000B
.equiv POVD2L, 0x000A
.equiv POVD1H, 0x0009
.equiv POVD1L, 0x0008
; Low Byte (Even Address)
; Bit Positions defined below:
.equiv POUT3H, 0x0005
.equiv POUT3L, 0x0004
.equiv POUT2H, 0x0003
.equiv POUT2L, 0x0002
.equiv POUT1H, 0x0001
.equiv POUT1L, 0x0000
;==============================================================================
;
; 9. Inter-Integrated Circuit(I2C) Module Bit Position Definitions for SFRs
; & SFR High/Low byte definitions.
;==============================================================================
; 9a. SFR Definitions
;------------------------------------------------------------------------------
.equiv I2CRCVL, _I2CRCV
.equiv I2CRCVH, _I2CRCV+1
.equiv I2CTRNL, _I2CTRN
.equiv I2CTRNH, _I2CTRN+1
.equiv I2CBRGL, _I2CBRG
.equiv I2CBRGH, _I2CBRG+1
.equiv I2CCONL, _I2CCON ; See I2CCON description in
.equiv I2CCONH, _I2CCON+1 ; section 9b
.equiv I2CSTATL, _I2CSTAT ; See I2CSTAT description in
.equiv I2CSTATH, _I2CSTAT+1 ; section 9b
.equiv I2CADDL, _I2CADD
.equiv I2CADDH, _I2CADD+1
;------------------------------------------------------------------------------
; 9b. Bit Position Definitions for some SFRs
;------------------------------------------------------------------------------
; I2CCON : I2C Control Register
;------------------------------------------------------------------------------
; High Byte (Odd Address)
; Bit Positions defined below:
.equiv I2CEN, 0x000F
.equiv I2CSIDL, 0x000D
.equiv SCLREL, 0x000C
.equiv IPMIEN, 0x000B
.equiv A10M, 0x000A
.equiv DISSLW, 0x0009
.equiv SMEN, 0x0008
; Low Byte (Even Address)
; Bit Positions defined below:
.equiv GCEN, 0x0007
.equiv STREN, 0x0006
.equiv ACKDT, 0x0005
.equiv ACKEN, 0x0004
.equiv RCEN, 0x0003
.equiv PEN, 0x0002
.equiv RSEN, 0x0001
.equiv SEN, 0x0000
;------------------------------------------------------------------------------
; I2CSTAT : I2C Status Register
;------------------------------------------------------------------------------
; High Byte (Odd Address)
; Bit Positions defined below:
.equiv ACKSTAT, 0x000F
.equiv TRSTAT, 0x000E
.equiv BCL, 0x000A
.equiv GCSTAT, 0x0009
.equiv ADD10, 0x0008
; Low Byte (Even Address)
; Bit Positions defined below:
.equiv IWCOL, 0x0007
.equiv I2COV, 0x0006
.equiv D_A, 0x0005
.equiv P, 0x0004
.equiv S, 0x0003
.equiv R_W, 0x0002
.equiv RBF, 0x0001
.equiv TBF, 0x0000
;==============================================================================
;
; 10. UARTx Module Bit Position Definitions for SFRs
; & SFR High/Low byte definitions.
;==============================================================================
; 10a. SFR Definitions
;------------------------------------------------------------------------------
;------------------UART 1 Module-----------------------------------------------
.equiv U1MODEL, _U1MODE ; See U1MODE description in
.equiv U1MODEH, _U1MODE+1 ; sub-section below
.equiv U1STAL, _U1STA ; See U1STA description in
.equiv U1STAH, _U1STA+1 ; sub-section below
.equiv U1TXREGL, _U1TXREG
.equiv U1TXREGH, _U1TXREG+1
.equiv U1RXREGL, _U1RXREG
.equiv U1RXREGH, _U1RXREG+1
.equiv U1BRGL, _U1BRG
.equiv U1BRGH, _U1BRG+1
;------------------------------------------------------------------------------
; 10b. Bit Position Definitions for some SFRs
;------------------------------------------------------------------------------
; UxMODE : UART x Mode Register
;------------------------------------------------------------------------------
; High Byte (Odd Address)
; Bit Positions defined below:
.equiv UARTEN, 0x000F
.equiv USIDL, 0x000D
.equiv ALTIO, 0x000A
; Low Byte (Even Address)
; Bit Positions defined below:
.equiv WAKE, 0x0007
.equiv LPBACK, 0x0006
.equiv ABAUD, 0x0005
.equiv PDSEL1, 0x0002
.equiv PDSEL0, 0x0001
.equiv STSEL, 0x0000
;------------------------------------------------------------------------------
; U1STA : UART 1 Status and Control Register
;------------------------------------------------------------------------------
; High Byte (Odd Address)
; Bit Positions defined below:
.equiv UTXISEL, 0x000F
.equiv UTXBRK, 0x000B
.equiv UTXEN, 0x000A
.equiv UTXBF, 0x0009
.equiv TRMT, 0x0008
; Low Byte (Even Address)
; Bit Positions defined below:
.equiv URXISEL1, 0x0007
.equiv URXISEL0, 0x0006
.equiv ADDEN, 0x0005
.equiv RIDLE, 0x0004
.equiv PERR, 0x0003
.equiv FERR, 0x0002
.equiv OERR, 0x0001
.equiv URXDA, 0x0000
;==============================================================================
;
; 11. Serial Peripheral Interface Module Bit Position Definitions for SFRs
; & SFR High/Low byte definitions. (SPI1)
;==============================================================================
; 11a. SFR Definitions
;------------------------------------------------------------------------------
;------------------SPI 1 Module------------------------------------------------
.equiv SPI1STATL, _SPI1STAT ; See SPIxSTAT description in
.equiv SPI1STATH, _SPI1STAT+1 ; sub-section below
.equiv SPI1CONL, _SPI1CON ; See SPIxCON description in
.equiv SPI1CONH, _SPI1CON+1 ; sub-section below
.equiv SPI1BUFL, _SPI1BUF
.equiv SPI1BUFH, _SPI1BUF+1
;------------------------------------------------------------------------------
; 11b. Bit Position Definitions for some SFRs
;------------------------------------------------------------------------------
; SPI1STAT : SPI 1 Status register
;------------------------------------------------------------------------------
; High Byte (Odd Address)
; Bit Positions defined below:
.equiv SPIEN, 0x000F
.equiv SPISIDL, 0x000D
; Low Byte (Even Address)
; Bit Positions defined below:
.equiv SPIROV, 0x0006
.equiv SPITBF, 0x0001
.equiv SPIRBF, 0x0000
;------------------------------------------------------------------------------
; SPIxCON : SPI 1 Control Register
;------------------------------------------------------------------------------
; High Byte (Odd Address)
; Bit Positions defined below:
.equiv FRMEN, 0x000E
.equiv SPIFSD, 0x000D
.equiv DISSDO, 0x000B
.equiv MODE16, 0x000A
.equiv SMP, 0x0009
.equiv CKE, 0x0008
; Low Byte (Even Address)
; Bit Positions defined below:
.equiv SSEN, 0x0007
.equiv CKP, 0x0006
.equiv MSTEN, 0x0005
.equiv SPRE2, 0x0004
.equiv SPRE1, 0x0003
.equiv SPRE0, 0x0002
.equiv PPRE1, 0x0001
.equiv PPRE0, 0x0000
;==============================================================================
;
; 12. A/D Module Bit Position Definitions for SFRs
; & SFR High/Low byte definitions.
;==============================================================================
; 12a. SFR Definitions
;------------------------------------------------------------------------------
.equiv ADCBUF0L, _ADCBUF0
.equiv ADCBUF0H, _ADCBUF0+1
.equiv ADCBUF1L, _ADCBUF1
.equiv ADCBUF1H, _ADCBUF1+1
.equiv ADCBUF2L, _ADCBUF2
.equiv ADCBUF2H, _ADCBUF2+1
.equiv ADCBUF3L, _ADCBUF3
.equiv ADCBUF3H, _ADCBUF3+1
.equiv ADCBUF4L, _ADCBUF4
.equiv ADCBUF4H, _ADCBUF4+1
.equiv ADCBUF5L, _ADCBUF5
.equiv ADCBUF5H, _ADCBUF5+1
.equiv ADCBUF6L, _ADCBUF6
.equiv ADCBUF6H, _ADCBUF6+1
.equiv ADCBUF7L, _ADCBUF7
.equiv ADCBUF7H, _ADCBUF7+1
.equiv ADCBUF8L, _ADCBUF8
.equiv ADCBUF8H, _ADCBUF8+1
.equiv ADCBUF9L, _ADCBUF9
.equiv ADCBUF9H, _ADCBUF9+1
.equiv ADCBUFAL, _ADCBUFA
.equiv ADCBUFAH, _ADCBUFA+1
.equiv ADCBUFBL, _ADCBUFB
.equiv ADCBUFBH, _ADCBUFB+1
.equiv ADCBUFCL, _ADCBUFC
.equiv ADCBUFCH, _ADCBUFC+1
.equiv ADCBUFDL, _ADCBUFD
.equiv ADCBUFDH, _ADCBUFD+1
.equiv ADCBUFEL, _ADCBUFE
.equiv ADCBUFEH, _ADCBUFE+1
.equiv ADCBUFFL, _ADCBUFF
.equiv ADCBUFFH, _ADCBUFF+1
.equiv ADCON1L, _ADCON1 ; See ADCON1L through ADPCFGH
.equiv ADCON1H, _ADCON1+1 ; description in sub-section below
.equiv ADCON2L, _ADCON2
.equiv ADCON2H, _ADCON2+1
.equiv ADCON3L, _ADCON3
.equiv ADCON3H, _ADCON3+1
.equiv ADCHSL, _ADCHS
.equiv ADCHSH, _ADCHS+1
.equiv ADPCFGL, _ADPCFG
.equiv ADPCFGH, _ADPCFG+1
.equiv ADCSSLL, _ADCSSL
.equiv ADCSSLH, _ADCSSL+1
;------------------------------------------------------------------------------
; 12b. Bit Position Definitions for some SFRs
;------------------------------------------------------------------------------
; ADCON1 : A/D Control Register 1
;------------------------------------------------------------------------------
; High Byte (Odd Address)
; Bit Positions defined below:
.equiv ADON, 0x000F
.equiv ADSIDL, 0x000D
.equiv FORM1, 0x0009
.equiv FORM0, 0x0008
; Low Byte (Even Address)
; Bit Positions defined below:
.equiv SSRC2, 0x0007
.equiv SSRC1, 0x0006
.equiv SSRC0, 0x0005
.equiv SIMSAM, 0x0003
.equiv ASAM, 0x0002
.equiv SAMP, 0x0001
.equiv DONE, 0x0000
;------------------------------------------------------------------------------
; ADCON2 : A/D Control Register 2
;------------------------------------------------------------------------------
; High Byte (Odd Address)
; Bit Positions defined below:
.equiv VCFG2, 0x000F
.equiv VCFG1, 0x000E
.equiv VCFG0, 0x000D
.equiv CSCNA, 0x000A
.equiv CHPS1, 0x0009
.equiv CHPS0, 0x0008
; Low Byte (Even Address)
; Bit Positions defined below:
.equiv BUFS, 0x0007
.equiv SMPI3, 0x0005
.equiv SMPI2, 0x0004
.equiv SMPI1, 0x0003
.equiv SMPI0, 0x0002
.equiv BUFM, 0x0001
.equiv ALTS, 0x0000
;------------------------------------------------------------------------------
; ADCON3 : A/D Control Register 3
;------------------------------------------------------------------------------
; High Byte (Odd Address)
; Bit Positions defined below:
.equiv SAMC4, 0x000C
.equiv SAMC3, 0x000B
.equiv SAMC2, 0x000A
.equiv SAMC1, 0x0009
.equiv SAMC0, 0x0008
; Low Byte (Even Address)
; Bit Positions defined below:
.equiv ADRC, 0x0007
.equiv ADCS5, 0x0005
.equiv ADCS4, 0x0004
.equiv ADCS3, 0x0003
.equiv ADCS2, 0x0002
.equiv ADCS1, 0x0001
.equiv ADCS0, 0x0000
;------------------------------------------------------------------------------
; ADCHS : A/D Input Channel Select Register
;------------------------------------------------------------------------------
; High Byte (Odd Address)
; Bit Positions defined below:
.equiv CH123NB1, 0x000F
.equiv CH123NB0, 0x000E
.equiv CH123SB, 0x000D
.equiv CH0NB, 0x000C
.equiv CH0SB3, 0x000B
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