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ARM Macro Assembler Page 1
1 00000000 ;*
2 00000000 ;* File: os_cpu_a.s
3 00000000 ;*
4 00000000 ;* (c) Copyright ARM Limited 1999. All right
s reserved.
5 00000000 ;*
6 00000000 ;* ARM Specific code
7 00000000 ;*
8 00000000 ;*
9 00000000 ;
10 00000000 ; Functions defined in this module:
11 00000000 ;
12 00000000 ; void ARMDisableInt(void) /* disable interrupts when in
SVC */
13 00000000 ; void ARMEnableInt(void) /* enable interrupts when in
SVC */
14 00000000 ; void OSCtxSw(void) /* context switch */
15 00000000 ; void OSStartHighRdy(void) /* start highest priority ta
sk */
16 00000000
17 00000000 00000080
NoInt EQU 0x80
18 00000000
19 00000000 00002000
BIT_TIMER0
EQU (0x1<<13)
20 00000000 00000400
BIT_TIMER3
EQU (0x1<<10)
21 00000000 00000100
BIT_TIMER5
EQU (0x1<<8)
22 00000000 00000010
BIT_SIO EQU (0x1<<4)
23 00000000 00200000
BIT_EINT4567
EQU (0x1<<21)
24 00000000
25 00000000 01E00024
I_ISPC EQU 0x1e00024
26 00000000 01E0000C
INTMSK EQU 0x1e0000c
27 00000000 01D20054
EXTINTPND
EQU 0x1d20054
28 00000000
29 00000000 AREA |Assembly$$code|, CODE, READONLY
30 00000000 EXPORT TickHandler
31 00000000
32 00000000
33 00000000 ;:::::::::::::::::::::::::::::::::::::::::::::::::::::::
:::::::::::::::::::::::
34 00000000 ;-------------------------------------------------------
35 00000000 ; uC/OS Porting Core Function : ARMDisableInt
36 00000000 ;:::::::::::::::::::::::::::::::::::::::::::::::::::::::
:::::::::::::::::::::::
37 00000000
38 00000000 EXPORT ARMDisableInt
ARM Macro Assembler Page 2
39 00000000
40 00000000 ARMDisableInt
41 00000000 E92D0001 STMDB sp!, {r0}
42 00000004 E10F0000 MRS r0, CPSR
43 00000008 E3800080 ORR r0, r0, #NoInt
44 0000000C E12FF000 MSR CPSR_cxsf, r0
45 00000010 E8BD0001 LDMIA sp!, {r0}
46 00000014 E1A0F00E MOV pc, lr
47 00000018
48 00000018 ;:::::::::::::::::::::::::::::::::::::::::::::::::::::::
:::::::::::::::::::::::
49 00000018 ;-------------------------------------------------------
50 00000018 ; uC/OS Porting Core Function : ARMEnableInt
51 00000018 ;:::::::::::::::::::::::::::::::::::::::::::::::::::::::
:::::::::::::::::::::::
52 00000018
53 00000018 EXPORT ARMEnableInt
54 00000018
55 00000018 ARMEnableInt
56 00000018 E92D0001 STMDB sp!, {r0}
57 0000001C E10F0000 MRS r0, CPSR
58 00000020 E3C00080 BIC r0, r0, #NoInt
59 00000024 E12FF000 MSR CPSR_cxsf, r0
60 00000028 E8BD0001 LDMIA sp!, {r0}
61 0000002C E1A0F00E MOV pc, lr
62 00000030
63 00000030 ;:::::::::::::::::::::::::::::::::::::::::::::::::::::::
:::::::::::::::::::::::
64 00000030 ;-------------------------------------------------------
65 00000030 ; uC/OS Porting Core Function : OSStartHighRdy
66 00000030 ;:::::::::::::::::::::::::::::::::::::::::::::::::::::::
:::::::::::::::::::::::
67 00000030
68 00000030 IMPORT OSTaskSwHook
69 00000030 IMPORT OSRunning
70 00000030 IMPORT OSTCBHighRdy
71 00000030
72 00000030 EXPORT OSStartHighRdy
73 00000030
74 00000030 OSStartHighRdy
75 00000030 EBFFFFFE BL OSTaskSwHook ; Call user defined task sw
itch hook
76 00000034
77 00000034 E59F0188 LDR r0, =OSRunning ; Indicate that multitask
ing has started
78 00000038 E3A01001 MOV r1, #1
79 0000003C E5C01000 STRB r1, [r0]
80 00000040
81 00000040 E59F0180 LDR r0, =OSTCBHighRdy ; r0 <= &OSTCBHighRdy
82 00000044 E5900000 LDR r0, [r0] ; r0 <= OSTCBHighRdy
83 00000048
84 00000048 E590D000 LDR sp, [r0] ; sp <= OSTCBHighRdy->OSTCB
StkPtr
85 0000004C
86 0000004C E8BD0001 LDMFD sp!, {r0} ; restore SP...
87 00000050 E12EF000 MSR CPSR_xsf, r0
ARM Macro Assembler Page 3
88 00000054 E8BDDFFF LDMFD sp!, {r0-r12, lr, pc} ; Load task's cont
ext & Run task
89 00000058
90 00000058 ;:::::::::::::::::::::::::::::::::::::::::::::::::::::::
:::::::::::::::::::::::
91 00000058 ;-------------------------------------------------------
-
92 00000058 ; uC/OS Porting Core Function : OSCtxSw
93 00000058 ;:::::::::::::::::::::::::::::::::::::::::::::::::::::::
:::::::::::::::::::::::
94 00000058
95 00000058 IMPORT OSTCBCur
96 00000058 IMPORT OSTaskSwHook
97 00000058 IMPORT OSTCBHighRdy
98 00000058 IMPORT OSPrioCur
99 00000058 IMPORT OSPrioHighRdy
100 00000058
101 00000058 EXPORT OSCtxSw
102 00000058
103 00000058 OSCtxSw
104 00000058 E92D4000 STMFD sp!, {lr} ; push resume address
105 0000005C E92D5FFF STMFD sp!, {r0-r12, lr} ; push rest context
106 00000060 E10F0000 MRS r0, CPSR
107 00000064 E92D0001 STMFD sp!, {r0} ; push CPSR
108 00000068
109 00000068 E59F015C LDR r0, =OSTCBCur ; r0 <= &OSTCBCur
110 0000006C E5900000 LDR r0, [r0] ; r0 <= OSTCBCur
111 00000070 E580D000 STR sp, [r0] ; OSTCBCur->OSTCBStkPtr = sp
112 00000074
113 00000074 EBFFFFFE BL OSTaskSwHook ; Call user defined task sw
itch hook
114 00000078
115 00000078 E59F014C LDR r0, =OSTCBCur ; r0 <= &OSTCBCur
116 0000007C E59F1144 LDR r1, =OSTCBHighRdy ; r1 <= &OSTCBHighRdy
117 00000080
118 00000080 E5912000 LDR r2, [r1] ; r2 <= OSTCBHighRdy
119 00000084 E5802000 STR r2, [r0] ; OSTCBCur = OSTCBHighRdy
120 00000088
121 00000088 E59F0140 LDR r0, =OSPrioCur ; r0 <= &OSPrioCur
122 0000008C E59F1140 LDR r1, =OSPrioHighRdy
; r1 <= &OSPrioHighRdy
123 00000090
124 00000090 E5D13000 LDRB r3, [r1] ; r3 <= OSPrioHighRdy
125 00000094 E5C03000 STRB r3, [r0] ; OSPrioCur = OSPrioHighRdy
126 00000098
127 00000098 E592D000 LDR sp, [r2] ; sp <= OSTCBHighRdy->OSTCB
StkPtr
128 0000009C
129 0000009C E8BD0001 LDMFD sp!, {r0} ; restore SP...
130 000000A0 E12EF000 MSR CPSR_xsf, r0
131 000000A4 E8BDDFFF LDMFD sp!, {r0-r12, lr , pc} ; Load task's con
text & Run task
132 000000A8
133 000000A8
134 000000A8 ;:::::::::::::::::::::::::::::::::::::::::::::::::::::::
:::::::::::::::::::::::
135 000000A8 ;-------------------------------------------------------
-
ARM Macro Assembler Page 4
136 000000A8 ; uC/OS Porting Core Function : OSIntCtxSw
137 000000A8 ;:::::::::::::::::::::::::::::::::::::::::::::::::::::::
:::::::::::::::::::::::
138 000000A8
139 000000A8 IMPORT OSTCBCur
140 000000A8 IMPORT OSTaskSwHook
141 000000A8 IMPORT OSTCBHighRdy
142 000000A8 IMPORT OSPrioCur
143 000000A8 IMPORT OSPrioHighRdy
144 000000A8
145 000000A8 EXPORT OSIntCtxSw
146 000000A8
147 000000A8 OSIntCtxSw
148 000000A8 E59F0128 LDR r0, =SAVED_SVC_SP
149 000000AC E5901000 LDR r1, [r0]
150 000000B0
151 000000B0 E59F0114 LDR r0, =OSTCBCur ; r0 <= &OSCTBCur
152 000000B4 E5900000 LDR r0, [r0] ; r0 <= OSCTBCur
153 000000B8
154 000000B8 E5801000 STR r1, [r0] ; OSTCBCur->OSTCBStkPtr = sp
155 000000BC
156 000000BC EBFFFFFE BL OSTaskSwHook ; Call user defined task sw
itch hook
157 000000C0
158 000000C0 E59F0104 LDR r0, =OSTCBCur ; r0 <= &OSTCBCur
159 000000C4 E59F10FC LDR r1, =OSTCBHighRdy ; r1 <= &OSTCBHighRdy
160 000000C8
161 000000C8 E5912000 LDR r2, [r1] ; r2 <= OSTCBHighRdy
162 000000CC E5802000 STR r2, [r0] ; OSTCBCur = OSTCBHighRdy
163 000000D0
164 000000D0 E59F00F8 LDR r0, =OSPrioCur ; r0 <= &OSPrioCur
165 000000D4 E59F10F8 LDR r1, =OSPrioHighRdy
; r1 <= &OSPrioHighRdy
166 000000D8
167 000000D8 E5D13000 LDRB r3, [r1] ; r3 <= OSPrioHighRdy
168 000000DC E5C03000 STRB r3, [r0] ; OSPrioCur = OSPrioHighRdy
169 000000E0
170 000000E0 E592D000 LDR sp, [r2] ; sp <= OSTCBHighRdy->OSTCB
StkPtr
171 000000E4
172 000000E4 ;在不打开中断的情况下，进行任务切换
173 000000E4 E8BD0001 LDMFD sp!, {r0}
174 000000E8 E12EF000 MSR CPSR_xsf, r0
175 000000EC E8BDDFFF LDMFD sp!, {r0-r12, lr, pc} ; * the interrupt
is enable after executing th
is sentence
176 000000F0
177 000000F0 ;:::::::::::::::::::::::::::::::::::::::::::::::::::::::
:::::::::::::::::::::::
178 000000F0 ;-------------------------------------------------------
179 000000F0 ; uC/OS Porting Core Function : ExIntHandler4567
180 000000F0 ;:::::::::::::::::::::::::::::::::::::::::::::::::::::::
:::::::::::::::::::::::
181 000000F0
182 000000F0 IMPORT OSIntNesting
183 000000F0 IMPORT OSTimeTick
ARM Macro Assembler Page 5
184 000000F0 IMPORT OSIntExit
185 000000F0
186 000000F0 IntExit
187 000000F0 E12FF003 MSR CPSR_cxsf, r3
188 000000F4 E892800F LDMFD r2, {r0-r3, pc} ; do not execute the ISR
to prevent pumping the stac
k
189 000000F8
190 000000F8 EXPORT TickHandler
191 000000F8 TickHandler
192 000000F8 E24EE004 SUB lr, lr, #4
193 000000FC E92D400F STMFD sp!, {r0-r3, lr} ; push r0-r3, pc
194 00000100
195 00000100 E59F00D4 LDR r0, =I_ISPC
196 00000104 E3A01F40 LDR r1, =BIT_TIMER5
197 00000108 E5801000 STR r1, [r0] ; clear the interrupt pendin
g bit
198 0000010C
199 0000010C E1A0100E MOV r1, lr ; r1 <- return pc
200 00000110 E1A0200D MOV r2, sp ; r2 <- sp_irq
201 00000114 E28DD014 ADD sp, sp, #20 ; adjust the sp
202 00000118
203 00000118 ;............ Added for the sake of preventing interrupt
nesting ................
204 00000118 E14F3000 mrs r3, spsr ; r3 <- spsr_irq
205 0000011C E3830080 orr r0, r3, #0x80 ; mask the interrupt
206 00000120 E169F000 msr spsr_cf, r0 ; change spsr_irq
207 00000124 ;.......................................................
.........................
208 00000124
209 00000124 E59F00B4 LDR r0,=IRQ_2
210 00000128 E1B0F000 MOVS pc,r0 ; At this point, cpsr_svc :=
spsr_irq...
211 0000012C IRQ_2
212 0000012C E59F00B0 ldr r0, =OSIntNesting
213 00000130 E5D00000 ldrb r0, [r0]
214 00000134 E3500008 cmp r0, #8
215 00000138 2AFFFFFE bcs IntExit ; 如果OSIntNesting>8, IntExi
t
216 0000013C E3500000 CMP r0, #0
217 00000140 0A000006 BEQ %F1
218 00000144 0
219 00000144 E92D0002 stmfd sp!, {r1} ; push SVC's pc to task stac
k
220 00000148 E92D5FF0 stmfd sp!, {r4-r12,lr} ; push SVC's r14, r12-r
4 to task stack
221 0000014C E1A07003 mov r7, r3 ; cpsr
222 00000150 E892000F ldmfd r2, {r0-r3} ; pop r0~r3 in irq stack
223 00000154 E92D000F stmfd sp!, {r0-r3} ; push r0~r3 to task stack
224 00000158 E92D0080 stmfd sp!, {r7} ; push cpsr to task stack
225 0000015C EA000009 B %F2
226 00000160
227 00000160 1
228 00000160 E92D0002 stmfd sp!, {r1} ; push SVC's pc to task stac
k
229 00000164 E92D5FF0 stmfd sp!, {r4-r12,lr} ; push SVC's r14, r12-r
4 to task stack
230 00000168 E1A07003 mov r7, r3 ; cpsr
231 0000016C E892000F ldmfd r2, {r0-r3} ; pop r0~r3 in irq stack
ARM Macro Assembler Page 6
232 00000170 E92D000F stmfd sp!, {r0-r3} ; push r0~r3 to task stack
233 00000174 E92D0080 stmfd sp!, {r7} ; push cpsr to task stack
234 00000178
235 00000178 E59F0058 LDR r0, =SAVED_SVC_SP
236 0000017C E580D000 STR sp, [r0]
237 00000180 E59F0060 LDR r0, =IntReStackTop
238 00000184 E1A0D000 MOV sp, r0
239 00000188
240 00000188 2
241 00000188 E59F0054 LDR r0, =OSIntNesting
; Notify uC/OS-II of ISR
242 0000018C E5D01000 LDRB r1, [r0]
243 00000190 E2811001 ADD r1, r1, #1 ;OSIntNesting++
244 00000194 E5C01000 STRB r1, [r0]
245 00000198
246 00000198 EBFFFFFE BL OSTimeTick ; Process system tick
247 0000019C EBFFFFFE BL OSIntExit ; Notify uC/OS-II of end of
ISR
248 000001A0
249 000001A0 E59F003C LDR r0, =OSIntNesting
250 000001A4 E5D00000 LDRB r0, [r0]
251 000001A8 E3500000 CMP r0, #0
252 000001AC 1A000001 BNE %F1
253 000001B0
254 000001B0 E59F0020 LDR r0, =SAVED_SVC_SP
255 000001B4 E590D000 LDR sp, [r0]
256 000001B8
257 000001B8 1
258 000001B8 E8BD0001 LDMFD sp!, {r0}
259 000001BC E12FF000 MSR CPSR_cxsf, r0
260 000001C0 E8BDDFFF LDMFD sp!, {r0-r12, lr, pc}
; restore the context
261 000001C4
262 000001C4
263 000001C4
264 000001C4
265 000001C4
266 000001C4 00000000
00000000
00000000
00000000
00000000
00000000
01E00024
0000012C
00000000
00000000
00000000
00000000 AREA INT_DATA, DATA, READWRITE
267 00000000
268 00000000 00000000
SAVED_SVC_SP
DCD 0
269 00000004 00 00 00
00 00 00
00 00 00
00 00 00
00 00 00
00 00 00
ARM Macro Assembler Page 7
00 00 00
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ARM Macro Assembler Page 8
00 00 00
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