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📄 tms470r1b1m_can_01.c

📁 TMS470的CAN总线源码
💻 C
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//------------------------------------------------------------------------------
// tms470r1b1m_CAN_01.c - CAN Demo (Polling Version)
//
// Description: This demo code demonstrates the use of the High End CAN
// Controller 1 (HECC1) in polling mode. Multiple CAN nodes running this code
// example can be wired together, and will all toggle their LEDs when
// the button of any node is pressed.
//
// On Button press, a message with the standard msg ID of 0x400 is send out and
// the LED is toggled. When a message with the ID of 0x400 is received,
// the LED status is set according to the data field of the incoming message.
// 11-bit standard identifier messages are used.
//
//  SYSCLK = MCLK = ACLK = 8 x 7.3728MHz = 58.9824MHz
//  ICLK = SYSCLK / 2 = 29.4912MHz
//
//  //*An external 7.3728MHz XTAL with proper load caps is required*//	
//
//            TMS-FET470B1M
//          +---------------+
//          |          OSCIN|-
//       +--|PLLDIS         | 7.3728MHz
//       |  |         OSCOUT|-
//      -+- |               |
//          |           HET0|---> LED
//          |          GIOA4|<--- Button#1
//          |               |
//          |        CAN1HTX|---> CAN network, ~125kbit/s
//          |        CAN1HRX|<---
//          |          GIOA3|---> CAN transceiver enable
//          |               |
//          +---------------+
//
// Andreas Dannenberg / John Mangino
// Texas Instruments Inc.
// July 29th 2005
// Built with IAR Embedded Workbench Version: 4.30A
//------------------------------------------------------------------------------

#include "intrinsic.h"
#include "iotms470r1b1m.h"
#include "tms470r1b1m_bit_definitions.h"

unsigned int LED_State;

void CAN_Init(void);

void main(void)
{
  PCR = CLKDIV_2;                               // ICLK = SYSCLK / 2
  GCR = ZPLL_CLK_DIV_PRE_1;                     // SYSCLK = 8 x fOSC
  PCR |= PENABLE;                               // Enable peripherals

  HETDCLR = 0xffffffff;                         // Clear HET output latches
  HETDIR = 0xffffffff;                          // Set HET as GIO outputs

  GIODCLRA = 0x08;                              // Clear GIOA3 output latch to
                                                // enable ext. CAN transceiver
  GIODIRA = 0x08;                               // Set GIOA3 to output

  CAN_Init();                                   // Init High End CAN controller

  LED_State = 0;                                // Init LED status var

  while (1)                                     // Loop forever...
  {
    if (HECC1CANRMP & RMP0)                        // Msg pending in mailbox 0?
    {
      LED_State = HECC1CANMDL0 >> 24;              // Read new state from CAN msg

      if (LED_State)                            // Update LED
        HETDSET = 0x01;                         // LED on
      else
        HETDCLR = 0x01;                         // LED off

      HECC1CANRMP = RMP0;                          // Clear flag, new msg can be
    }                                           // received now

    if (!(GIODINA & 0x10))                      // Button 1 pressed?
    {
      LED_State ^= 0x01;                        // Toggle status var

      HECC1CANME &= ~ME1;                          // Disable mailbox 1
      HECC1CANMDL1 = LED_State << 24;              // Update msg data byte D0
      HECC1CANME |= ME1;                           // Re-enable mailbox 1

      HECC1CANTRS = TRS1;                          // Send message 1
      while (!(HECC1CANTA & TA1));                 // Wait for transmission end

      if (LED_State)                            // Update LED
        HETDSET = 0x01;                         // LED on
      else
        HETDCLR = 0x01;                         // LED off

      HECC1CANTA = TA1;                            // Clear TX ACK flag
      while (HECC1CANTA & TA1);                    // Wait for flag to be cleared

      for (volatile unsigned int i = 0; i < 500000; i++); // Button debounce
    }
  }
}
//------------------------------------------------------------------------------
// High End CAN controller initialization
//
// Sets up the CAN controller for operation at 125kbit/s. Two mailboxes are
// initialized for receiving (mailbox 0) and transmitting (mailbox 1) messages
// with a standard 11-bit ID of 0x400. No interrupts are used.
//------------------------------------------------------------------------------
void CAN_Init(void)
{
  // Use CAN1HTX pin for the CAN transmit functions
  HECC1CANTIOC = TXFUNC;

  // Use CAN1HRX pin for the CAN receive functions
  HECC1CANRIOC = RXFUNC;

  // Set global interrupt mask
  HECC1CANGIM = 0x00;

  // Setup master control register
  // Enable configuration mode, activate auto bus on after bus off condition
  HECC1CANMC = CCR + ABO;

  // Wait until CPU has access to CAN configuration registers
  while (!(HECC1CANES & CCE));

  // Setup CAN bit timing for ~125kbit/s
  // 8.07us nominal bit time w/ 17TQs/bit, sample point is located
  // at 7.12us (15TQ)
  // BRP = 13 (Prescaler 14, w/ ICLK = 29.4912MHz)
  // Sample 3x, TSEG1 = 14, TSEG2 = 2, SJW = 1
  HECC1CANBTC = (13 << 16) + SAM + TSEG1_14 + TSEG2_2 + SJW_1;

  // Setup local acceptance mask LAM0
  // Treat all incoming MID bits as significant
  HECC1CANLAM0 = 0x00 << 18;

  // Configure mailbox 0 for receive
  HECC1CANMID0 = AME + 0x400 << 18;                // Set ID for messages to RX,
  HECC1CANMCF0 = 0x00;                             // uses acceptance mask LAM0
  HECC1CANMDL0 = 0x00;
  HECC1CANMDH0 = 0x00;

  // Configure mailbox 1 for transmit
  HECC1CANMID1 = 0x400 << 18;                      // Set ID for msgs to transmit
  HECC1CANMCF1 = DLC_1;                            // Send one byte
  HECC1CANMDL1 = 0x00;
  HECC1CANMDH1 = 0x00;

  HECC1CANMD = MD0;                                // Use mbox 0 for RX, 1 for TX
  HECC1CANOPC = OPC0;                              // Protect against overwrite
  HECC1CANME = ME1 + ME0;                          // Enable mailboxes 1 and 0

  // Start CAN module
  HECC1CANMC &= ~CCR;

  // Wait until CAN module is started
  while (HECC1CANES & CCE);
}

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