syslib.c

嵌入式操作系统VxWorks中板级支持包文件

* This routine returns the address of the first missing byte of memory,
* which indicates the top of memory.
*
* RETURNS: The address of the top of memory.
*/

char *sysMemTop (void)
    {
/* TODO - If auto-sizing is possible, define in config.h */
#ifdef LOCAL_MEM_AUTOSIZE
/* auto-sizing is possible  */
    return ((char *)LOCAL_MEM_LOCAL_ADRS + (sysPhysMemSize () - LOCAL_MEM_RESERVED));
#else
/* Don't do autosizing, if size is given */
    return ((char *)LOCAL_MEM_LOCAL_ADRS + (LOCAL_MEM_SIZE - LOCAL_MEM_RESERVED));
#endif /* LOCAL_MEM_AUTOSIZE */
    }

/*******************************************************************************
*
* sysToMonitor - transfer control to the ROM monitor
*
* This routine transfers control to the ROM monitor.  It is usually called
* only by reboot() -- which services ^X -- and bus errors at interrupt
* level.  However, in some circumstances, the user may wish to introduce a
* new <startType> to enable special boot ROM facilities.
*
* startType - passed to ROM to tell it how to boot
*
* RETURNS: Does not return.
*/

STATUS sysToMonitor (int startType)
    {
    FUNCPTR     pRom;
#ifdef INCLUDE_PCI
    UINT32      tmp;
#endif

#ifdef INCLUDE_PCI
#ifdef INCLUDE_END
    END_OBJ * pEnd;
    UINT32      i;
#endif  /* INCLUDE_END */

#ifdef INCLUDE_END
    /*
     * If the Ethernet drivers were left alone, the controller chip might
     * alter memory, so we stop the controller before jumping to the bootrom.
     */

#ifdef INCLUDE_FEI_END
    for(i = 0; i < MAX_END_DEVS; i++)
        {
        if ( (pEnd = endFindByName ("fei", i)) != NULL)
            pEnd->pFuncTable->stop(pEnd->devObject.pDevice);
        }
#endif /* INCLUDE_FEI_END */

#ifdef INCLUDE_GEI_END
    for(i = 0; i < MAX_END_DEVS; i++)
        {
        if ( (pEnd = endFindByName ("gei", i)) != NULL)
            pEnd->pFuncTable->stop(pEnd->devObject.pDevice);
        }
#endif /* INCLUDE_GEI_END */
#endif  /* INCLUDE_END */

/* 
 * TODO -
 * Disable ATU, 
 * Disable the device,
 * Disable Outbound Transactions,
 * mask off ATU error ints, we must disable all IRQ causes 
 */
#endif

#ifdef INCLUDE_SERIAL
    sysSerialReset ();  /* put serial devices into quiet state */
#endif

    sysClkDisable();

    intIFLock ();

    sysINTCTL_MaskAll ();

    cacheArmXSCALEDClearDisable ();
    cacheArmXSCALEIClearDisable ();

    mmuArmXSCALETLBIDFlushAll ();
    mmuArmXSCALEADisable ();

    if (startType != BOOT_COLD)
        pRom = (FUNCPTR) (ROM_TEXT_ADRS + 4);   /* warm boot */
    else
        pRom = (FUNCPTR) ROM_TEXT_ADRS;         /* cold boot */

    (*pRom)(startType); /* jump to boot ROM */

    return OK;          /* in case we ever continue from ROM monitor */
    }

/*** BSP Info Routines ***/
/****************************************************************************
*
* sysProcNumGet - get the processor number
*
* This routine returns the processor number for the CPU board, which is
* set with sysProcNumSet().
*
* RETURNS: The processor number for the CPU board.
*
* SEE ALSO: sysProcNumSet()
*/

int sysProcNumGet (void)
    {
    return sysProcNum;
    }

/****************************************************************************
*
* sysProcNumSet - set the processor number
*
* Set the processor number for the CPU board.  Processor numbers should be
* unique on a single backplane.
*
* NOTE
* By convention, only processor 0 should dual-port its memory.
*
* RETURNS: N/A
*
* SEE ALSO: sysProcNumGet()
*/

void sysProcNumSet
    (
    int procNum		/* processor number */
    )
    {
    sysProcNum = procNum;
    }

/*******************************************************************************
*
* sysModel - return the model name of the CPU board
*
* This routine returns the model name of the CPU board.
*
* RETURNS: A pointer to a string identifying the board and CPU.
*/

char *sysModel (void)
    {
    /* TODO - fill in appropriate template model */
    return "Model-1";
    }

/*******************************************************************************
*
* sysBspRev - return the bsp version with the revision eg 1.1/<x>
*
* This function returns a pointer to a bsp version with the revision.
* for eg. 1.1/<x>. BSP_REV is concatanated to BSP_VERSION to form the
* BSP identification string.
*
* RETURNS: A pointer to the BSP version/revision string.
*/

char * sysBspRev (void)
    {
    return (BSP_VERSION BSP_REV);
    }

/* Wrappers */

/*
 * TODO - flush out interrupt routines in sysIntrCtl.c
 */

/********************************************************************************
* sysIntDisable - disable an interrupt level
*
* This routine disables a specified interrupt level.
*
* .nT
*
* RETURNS: OK, or ERROR if <intLevel> is out of range.
*
* SEE ALSO: sysIntEnable(),
* .sA
*/

STATUS sysIntDisable
    (
    int intLevel       /* interrupt level to disable */
    )
    {
     return (templateIntLvlDisable (intLevel)); /* see sysIntrCtl.c */
    }

/********************************************************************************
* sysIntEnable - enable an interrupt level
*
* This routine enables a specified interrupt level.
*
* .nT
*
* RETURNS: OK, or ERROR if <intLevel> is out of range.
*
* SEE ALSO: sysIntDisable(),
* .sA
*/

STATUS sysIntEnable
    (
    int intLevel       /* interrupt level to enable */
    )
    {
     return (templateIntLvlEnable (intLevel)); /* see sysIntrCtl.c */
    }

#ifdef INCLUDE_PCI
/********************************************************************************
* sysInitATU - initialize Address Translation Unit
*
* This routine initializes the Address Translation Unit.
*
* .nT
*
* RETURNS:
* .sA
*/

void sysInitATU (void)
{
  UINT32 memSize;
  UINT32 tmp;

    /* Perform Host ATU Initialization -
     *
     * These routine initializes the primary ATU, allowing template DRAM to be
     * accessible from the system bus.  The range requested is based on DRAM
     * size.
     */

/*
 * TODO - Perform Host ATU Initialization, such as...
 * Disable the device via ATU command reg,  
 * Disable Outbound Transactions, 
 * mask off ATU error ints, we must disable all IRQ causes,  
 * clear aborts, 
 * ATU Interrupt Status Register -clear,  
 *
 * Inbound:  
 * get top of system memory pool,    
 * set base address value to start of DRAM,  
 * set translate value to start of DRAM,  
 *
 * Outbound : 
 * PCI Memory Window 1 starts at 0x########,
 * PCI IO Window starts at 0x########,
 *
 * PCI-X Status Register,  
 * Bus Master Enable/Memory Enable,  
 * Enable Outbound Transactions,  
 * End ATU Initialization... 
 */

}
#endif

/*
 * TODO - setup a calibrated spin loop.
 *
 * In this example code, we assume that one pass of the spin
 * loop takes 1 microsecond for this BSP and processor.  Be sure
 * to use 'volatile' as appropriate to force the compiler to
 * not optimize your code.
 *
 * Must be interrupt safe.
 *
 */

/****************************************************************************
*
* sysUsDelay - delay at least the specified amount of time (in microseconds)
*
* This routine uses the terminal count capability of a spare timer and will 
* give only an approximate delay.
*
* This routine will delay for at least the specified amount of time using the
* lower 32 bit "word" of the Time Base register as the timer.  The accuracy of
* the delay increases as the requested delay increases due to a certain amount
* of overhead.
*
* NOTE:  This routine will not relinquish the CPU; it is meant to perform a
* busy loop delay.  The minimum delay that this routine will provide is
* approximately 1 microseconds.  The maximum delay is approximately the
* size of UINT32.
*
* NOMANUAL
*
* RETURNS: N/A
*/

void sysUsDelay
    (
    int         mSecs   /* delay */
    )
    {
    int         key;
    UINT32      countTicks;

/*
 * TODO - Perform microsecond delay routine via secondary timer...
 * I.E.:
 * total ticks = ((37.5MHz / 1000 ticks per second) * mSecs requested),
 */

    /* total ticks = ((37.5MHz / 1000 ticks per second) * mSecs requested) */
    countTicks = (sysClkRateGet () / 1000000) * mSecs;

    key = intLock ();

    /* disable timer 1 */
    sysDisable_TMR1 ();

    /* clear interrupts for timer 1 */
    sysClear_TISR1 ();

    /* 600MHz/16 = 37.5MHz, for 37.5Mhz clock */
    sysWrite_CSel_TMR1 (template_TMR_CSEL_CORE16);

    /*  Disable Timer 1 Auto Reload */
    sysDisable_Reload_TMR1 ();

    sysWrite_TCR1 (countTicks);

    /* enable timer 1 */
    sysEnable_TMR1 ();

    /* spin until terminal count bit set for timer 1 */
    while (!((*(volatile int *) template_TMR1_REG) & (0x1)))
        ;

    /* clear interrupts */
    sysClear_TISR1 ();

    /* disable timer 1 */
    sysDisable_TMR1 ();

    intUnlock (key);
    }

/*******************************************************************************
*
* cacheDmaXMalloc - allocate a cache-safe buffer when X-bit set
*
* cacheArchDmaMalloc returns the newly allocated buffer as non -cacheable,
* since this violates the 80200 spec for X-bit usage we need to provide a
* platform specific work around...
*
* This routine attempts to return a pointer to a section of memory
* that will not experience cache coherency problems.  This routine
* is only called when MMU support is available for cache control.
*
* RETURNS: A pointer to a cache-safe buffer, or NULL.
*
* NOMANUAL
*/

void * cacheDmaXMalloc
    (
    size_t  bytes   /* size of cache-safe buffer */
    )
    {
    void *  pBuf;
    int     pageSize;

    if ((pageSize = VM_PAGE_SIZE_GET ()) == ERROR)
    return NULL;

#if (!ARM_HAS_MPU)
    /* make sure bytes is a multiple of pageSize */

    bytes = ROUND_UP (bytes, pageSize);


    if ((_func_valloc == NULL) ||
    ((pBuf = (void *)(* _func_valloc) (bytes)) == NULL))
    return NULL;

#else /* (!ARM_HAS_MPU) */
    /*
     * On MPUs, regions must be aligned with their size, which must be
     * a power of two and at least 4k in size.
     */

    bytes = ROUND_UP (bytes, pageSize); /* round up to pageSize */


    /* round up to a power of two in size */

    bytes = ROUND_UP (bytes, (1 << (ffsMsb(bytes) - 1)));

    if ((_func_memalign == NULL) ||
    ((pBuf = (void *)(* _func_memalign) (bytes, bytes)) == NULL))
    return NULL;

#endif /* !ARM_HAS_MPU) */

    /*
     * Note that on MPUs we need to specify VM_STATE_VALID here, in
     * order that a new region will be created, if necessary, and that
     * that region will be marked as active, with appropriate access
     * rights. We should also free the allocate buffer and return NULL
     * if the VM_STATE_SET call fails. Here we set the cacheable & bufferable
     * bits under X-bit support. This fixes SPR #74186.
     */

    if (VM_STATE_SET (NULL, pBuf, bytes,
          VM_STATE_MASK_EX_CACHEABLE | VM_STATE_MASK_EX_BUFFERABLE | VM_STATE_MASK_VALID,
          VM_STATE_EX_CACHEABLE_NOT | VM_STATE_EX_BUFFERABLE_NOT | VM_STATE_VALID) != OK)
        {
    free (pBuf);
    return NULL;
    }

    return pBuf;

    } /* cacheDmaXMalloc() */

#ifdef INCLUDE_PCI
/*****************************/
/* For Quick scan of PCI Bus */
/*****************************/
void sysPciProbe (void)
{
  UINT8 nDevNo;

  for (nDevNo = 0 ;nDevNo < 16 ;nDevNo++)
    printf ("Device No %d Vendor Id 0x%x\n\n", nDevNo, pciCfgRd (nDevNo, 0));
}

/*
 * TODO -
 * supply correct OCCAR & OCCDR reg definitions for template
 */

UINT32 pciCfgRd (UINT8 nDevNo, UINT8 nRegNo)
{
  UINT32 nRetValue;
  UINT32 idSel;

  idSel = ((1 << (nDevNo + 16)) | (nDevNo << 11) | (nRegNo << 2));
  *((volatile UINT32 *)(template_OCCAR_REG)) = idSel;

  printf ("pciTest: Probing idSel 0x%x\n", idSel);

  if (vxMemProbe ((char*)template_OCCDR_REG, VX_READ, 4, (char*)&nRetValue) == OK)
    return (*(volatile UINT32 *)(template_OCCDR_REG));
  else
    return (-1);
}
#endif