sysfei82557end.c

嵌入式操作系统VxWorks中板级支持包文件

		{
		printf ("i82557(%d): Invalid EEPROM checksum %#4.4x\n", unit, sum);
		}
	    
		/* DP83840 specific setup */
		if(((pRes->eeprom[6]>>8) & 0x3f) == DP83840)
		{
		int reg23 = sys557mdioRead (unit, pRes->eeprom[6] & 0x1f, 23);
		sys557mdioWrite (unit, pRes->eeprom[6] & 0x1f, 23, reg23 | 0x0420);
		}
	}
    else if(pRes->eeprom[0] == 0xffff && pRes->eeprom[1] == 0xffff && pRes->eeprom[2] == 0xffff)
	{
		memcpy((void*)pRes->eeprom,(void*)i82559erMacAddr,6);
	}
		
    /* perform a system self-test. */
    pRes->timeout     = 16000;		/* Timeout for set-test. */

    /*
     * No specific area specified, so we assume that cacheDmaMalloc() will
     * return a pointer to a suitable area. If the data cache is on,
     * this will be page-aligned, but if the data cache is off, then we
     * will just get whatever malloc returns.
     */

    if (testbuf = cacheDmaMalloc (32), testbuf == 0)
     {
      printf("fei%d cacheDmaMalloc failed\n", unit);
      return ERROR;
     }
    pRes->pResults = (volatile INT32 *)testbuf;

    /* The chip requires the results buffer to be 16-byte aligned. */

    pRes->pResults    = (volatile INT32 *) ((((int) pRes->pResults) + 0xf) & ~0xf);

    pRes->pResults[0] = 0;
    pRes->pResults[1] = -1;

    /* Issue the self-test command */

    /*
     * If using cacheDmaMalloc() it will return a "low-alias" address in
     * SDRAM, and this will need converting to a "high-alias"
     * address, so it can be accessed from the PCI bus.
     */

    sysOutLong (pRes->iobaseCsr + SCB_PORT, (int)pRes->pResults | 1);

    /* wait for results */
    do
     {
      sys557Delay ();         /* cause a delay of at least an I/O cycle */
     } while ((pRes->pResults[1] == -1) && (--pRes->timeout >= 0));

    /* Save results so we can refer to them again later */

    pRes->str[0] = pRes->pResults[0];
    pRes->str[1] = pRes->pResults[1];

    cacheDmaFree (testbuf);

    pRes->pResults = pRes->str;

    /* initialize the board information structure */
    pBoard->vector    = pRes->irq;
    pBoard->baseAddr  = pRes->membaseCsr;	/* Using PCI mem space is better */

    for (ix = 0, iy = 0; ix < 3; ix++)
    {
	pBoard->enetAddr[iy++] = pRes->eeprom[ix] & 0xff;
	pBoard->enetAddr[iy++] = (pRes->eeprom[ix] >> 8) & 0xff;
    }
	
    pBoard->intEnable     = sys557IntEnable;
    pBoard->intDisable    = sys557IntDisable;
    pBoard->intAck        = sys557IntAck;
    pBoard->sysLocalToBus = NULL;
    pBoard->sysBusToLocal = NULL;

#ifdef FEI_10MB
    pBoard->phySpeed = NULL;
    pBoard->phyDpx   = NULL;
#endif
    }

    return OK;
}

/***************************************************************************
*
* sys557IntAck - acknowledge an 82557 interrupt
*
* This routine performs any 82557 interrupt acknowledge that may be
* required.  This typically involves an operation to some interrupt
* control hardware.
*
* This routine gets called from the 82557 driver's interrupt handler.
*
* This routine assumes that the PCI configuration information has already
* been setup.
*
* RETURNS: OK, or ERROR if the interrupt could not be acknowledged.
*/

LOCAL STATUS sys557IntAck(int unit)
{
    return OK;
}

/*******************************************************************************
*
* sys557IntEnable - enable 82557 interrupts
*
* This routine enables 82557 interrupts.  This may involve operations on
* interrupt control hardware.
*
* The 82557 driver calls this routine throughout normal operation to terminate
* critical sections of code.
*
* This routine assumes that the PCI configuration information has already
* been setup.
*
* RETURNS: OK, or ERROR if interrupts could not be enabled.
*/

LOCAL STATUS sys557IntEnable(int unit)
{
SYS_FEI_RESOURCE *pRes = &feiResources [unit];

    intEnable(pRes->irq);
    return OK;
}

/*******************************************************************************
*
* sys557IntDisable - disable 82557 interrupts
*
* This routine disables 82557 interrupts.  This may involve operations on
* interrupt control hardware.
*
* The 82557 driver calls this routine throughout normal operation to enter
* critical sections of code.
*
* This routine assumes that the PCI configuration information has already
* been setup.
*
* RETURNS: OK, or ERROR if interrupts could not be disabled.
*/

LOCAL STATUS sys557IntDisable(int unit)
{
SYS_FEI_RESOURCE *pRes = &feiResources [unit];

    intDisable(pRes->irq);
    return OK;
}

/***************************************************************************
*
* sys557eepromRead - read a word from the 82557 EEPROM
*
* RETURNS: the EEPROM data word read in.
*/

LOCAL UINT16 sys557eepromRead
    (
    int unit,           /* unit number */
    int location        /* address of word to be read */
    )
{
    UINT32 iobase = feiResources[unit].membaseCsr;
    UINT16 retval = 0;
    UINT16 dataval;
    volatile UINT16 dummy;
    int ix;

    sysOutWord (iobase + SCB_EEPROM, EE_CS);	/* enable EEPROM */

    /* write the READ opcode */

    for (ix = EE_CMD_BITS - 1; ix >= 0; ix--){
        dataval = (EE_CMD_READ & (1 << ix)) ? EE_DI : 0;
        sysOutWord (iobase + SCB_EEPROM, EE_CS | dataval);
        sys557Delay ();    /* delay for one IO READ cycle */
        sysOutWord (iobase + SCB_EEPROM, EE_CS | dataval | EE_SK);
        sys557Delay ();    /* delay for one IO READ cycle */
        sysOutWord (iobase + SCB_EEPROM, EE_CS | dataval);
        sys557Delay ();    /* delay for one IO READ cycle */
    }

    /* write the location */

    for (ix = EE_ADDR_BITS - 1; ix >= 0; ix--){
        dataval = (location & (1 << ix)) ? EE_DI : 0;
        sysOutWord (iobase + SCB_EEPROM, EE_CS | dataval);
        sys557Delay ();    /* delay for one IO READ cycle */
        sysOutWord (iobase + SCB_EEPROM, EE_CS | dataval | EE_SK);
        sys557Delay ();    /* delay for one IO READ cycle */
        sysOutWord (iobase + SCB_EEPROM, EE_CS | dataval);
        sys557Delay ();    /* delay for one IO READ cycle */
	    dummy = sysInWord (iobase + SCB_EEPROM);
     }

    if((dummy & EE_DO) == 0)		/* dummy read */
	;

    /* read the data */
    for (ix = EE_DATA_BITS - 1; ix >= 0; ix--){
        sysOutWord (iobase + SCB_EEPROM, EE_CS | EE_SK);
        sys557Delay ();    /* delay for one IO READ cycle */
        retval = (retval << 1) | ((sysInWord (iobase + SCB_EEPROM) & EE_DO) ? 1 : 0);
        sysOutWord (iobase + SCB_EEPROM, EE_CS);
        sys557Delay ();    /* delay for one IO READ cycle */
    }

    sysOutWord (iobase + SCB_EEPROM, 0x00);	/* disable EEPROM */

    return retval;
}

/***************************************************************************
*
* sys557mdioRead - read MDIO
*
* RETURNS: read value
*/

LOCAL UINT32 sys557mdioRead
    (
    int unit,           /* unit number */
    int phyId,          /* PHY ID */
    int location        /* location to read */
    )
{
    UINT32 iobase = feiResources[unit].membaseCsr;
    int timeout   = 64*4;	/* <64 usec. to complete, typ 27 ticks */
    int val;

    sysOutLong (iobase + SCB_MDI, 0x08000000 | (location<<16) | (phyId<<21));
    do {
        sys557Delay ();    /* delay for one IO READ cycle */
    	val = sysInLong (iobase + SCB_MDI);
    	if (--timeout < 0)
    	    printf ("sys557mdioRead() timed out with val = %8.8x.\n", val);
    } while (! (val & 0x10000000));

    return (val & 0xffff);
}

/***************************************************************************
*
* sys557mdioWrite - write MDIO
*
* RETURNS: write value
*/

LOCAL UINT32 sys557mdioWrite
    (
    int unit,           /* unit number */
    int phyId,          /* PHY ID */
    int location,       /* location to write */
    int value           /* value to write */
    )
{
    UINT32 iobase = feiResources[unit].membaseCsr;
    int timeout   = 64*4;	/* <64 usec. to complete, typ 27 ticks */
    int val;

    sysOutLong (iobase + SCB_MDI, 0x04000000 | (location<<16) | (phyId<<21) | value);
    do{
        sys557Delay ();    /* delay for one IO READ cycle */
    	val = sysInLong (iobase + SCB_MDI);
    	if (--timeout < 0)
    	    printf ("sys557mdioWrite() timed out with val = %8.8x.\n", val);
    } while (! (val & 0x10000000));

    return (val & 0xffff);
}

/*******************************************************************************
*
* sys557Show - shows 82557 configuration
*
* this routine shows (Intel Pro Express 100) configuration
*
* RETURNS: N/A
*/

void sys557Show(int unit)
{
int	ix,iy,itype;
SYS_FEI_RESOURCE *pRes   = &feiResources [unit];
UINT32            iobase = pRes->membaseCsr;
UCHAR             etheraddr[6];

    if(unit > MAX_END_DEVS) 
    {
	printf ("Illegal unit number %d\n", unit);
	return;
    }

    for(itype = 0;itype < NELEMENTS(feiDevices);++itype)
    {
	if(feiDevices[itype].pciVend == 0 && feiDevices[itype].pciDevice == 0)
	{
	printf("Unit %d not an FEI device\n", unit);
	return;
	}

	if(feiDevices[itype].pciVend == pRes->pciVendID &&
	   feiDevices[itype].pciDevice == pRes->pciDevID)
	{
	break;
	}
    }

    for(ix = 0, iy = 0; ix < 3; ix++)
    {
        etheraddr[iy++] = pRes->eeprom[ix];
        etheraddr[iy++] = pRes->eeprom[ix] >> 8;
    }

    if (itype == 0)
     printf("82559(%d): Intel Pro 100B at %#8x ", (int)unit, (UINT32)iobase);
    else
     printf("82559(%d): Intel Pro 100S at %#8x ", (int)unit, (UINT32)iobase);
    
    for(ix = 0; ix < 5; ix++)
     printf ("%2.2X:", etheraddr[ix]);
    
    printf ("%2.2X\n", etheraddr[ix]);
    printf ("CSR mem base address = %x, Flash mem base address = %x\n",	pRes->membaseCsr, pRes->membaseFlash);

    if(pRes->pciDevID == PRO100B_PCI_DEVICE_ID) 
    {
        if (pRes->eeprom[3] & 0x03)
            printf ("Receiver lock-up bug exists -- enabling work-around.\n");

        printf ("Board assembly %4.4x%2.2x-%3.3d, Physical connectors present:",
	    pRes->eeprom[8], pRes->eeprom[9]>>8, pRes->eeprom[9] & 0xff);
        for (ix = 0; ix < 4; ix++)
	  if (pRes->eeprom[5] & (1 << ix))
	    printf ("%s", fei_connectors [ix]);

        printf ("\nPrimary interface chip %s PHY #%d.\n",
	           fei_phys[(pRes->eeprom[6]>>8)&7], pRes->eeprom[6] & 0x1f);
        if (pRes->eeprom[7] & 0x0700)
          printf ("Secondary interface chip %s.\n",fei_phys[(pRes->eeprom[7]>>8)&7]);
    }

    if (pRes->timeout < 0)
    {	/* Test optimized out. */
	printf ("Self test failed, status %8.8x:\n"
	        " Failure to initialize the 82557.\n"
	        " Verify that the card is a bus-master capable slot.\n",
	        pRes->pResults[1]);
    } 
    else 
    {
	printf ("General self-test: %s.\n"
                " Serial sub-system self-test: %s.\n"
                " Internal registers self-test: %s.\n"
                " ROM checksum self-test: %s (%#8.8x).\n",
                pRes->pResults[1] & 0x1000 ? "failed" : "passed",
                pRes->pResults[1] & 0x0020 ? "failed" : "passed",
                pRes->pResults[1] & 0x0008 ? "failed" : "passed",
                pRes->pResults[1] & 0x0004 ? "failed" : "passed",
                pRes->pResults[0]);
    }
}
#endif /* INCLUDE_FEI_END */