sysgei82544end.c

嵌入式操作系统VxWorks中板级支持包文件

    int          unit,
    UINT32       index
    )
    {
    UINT16 val;

    if (index >= EEPROM_WORD_SIZE)
        {
        printf ("Invalid index:%d to EEPROM\n", index);
        return 0;
        }

    GEI_SYS_WRITE_REG(unit, INTEL_82543GC_EECD, EECD_CS_BIT);

    /* wait */
    SYS_DELAY(10);

    /* write the opcode out */
    sys543eepromWriteBits (unit, EEPROM_READ_OPCODE, EEPROM_CMD_BITS);

    /* write the index out */
    sys543eepromWriteBits (unit, index, EEPROM_INDEX_BITS);

    /* read the data */
    val = sys543eepromReadBits (unit, EEPROM_DATA_BITS);

    /* clean up access to EEPROM */
    GEI_SYS_WRITE_REG(unit, INTEL_82543GC_EECD, 0);

    /* wait */
    SYS_DELAY(300);

    return val;
    }

/*************************************************************************
*
* sys543EtherAddrGet - Get Ethernet address from EEPROM
*
* This routine get an Ethernet address from EEPROM
*
* RETURNS: OK or ERROR
*/

LOCAL STATUS sys543EtherAddrGet
    (
    int unit
    )
    {
    UINT32 ix, count=0;
    UINT16 val;
    UCHAR  adr [ETHER_ADDRESS_SIZE];

    for (ix = 0; ix < ETHER_ADDRESS_SIZE / sizeof(UINT16); ix++)
        {
        /* get word i from EEPROM */
        val = sys543eepromReadWord (unit, (UINT16)(EEPROM_IA_ADDRESS + ix));
        adr [count++] = (UCHAR)val;
        adr [count++] = (UCHAR) (val >> 8);
        }

    /* check IA is UCAST  */
    if (adr[0] & 0x1)
        return (ERROR);

    memcpy (&geiResources[unit].enetAddr[0], adr, ETHER_ADDRESS_SIZE);

    return (OK);
    }

/**************************************************************************
*
* sys543eepromCheckSum - calculate checksum
*
* This routine perform EEPROM checksum
*
* RETURNS: N/A
*/

LOCAL STATUS sys543eepromCheckSum
    (
    int unit
    )
    {
    UINT16 checkSum = 0 ;
    UINT32 ix;

    for (ix = 0; ix < EEPROM_WORD_SIZE; ix++)
        checkSum += sys543eepromReadWord (unit, ix);

    if (checkSum == (UINT16)EEPROM_SUM)
        return OK;

    return ERROR;
    }

/**************************************************************************
*
* sys543PhySpecRegsInit - Initialize PHY specific registers
*
* This routine initialize PHY specific registers
*
* RETURN: N/A
*/

LOCAL void sys543PhySpecRegsInit
    (
    PHY_INFO * pPhyInfo,    /* PHY's info structure pointer */
    UINT8      phyAddr      /* PHY's bus number */
    )
    {
    UINT16 regVal;          /* register value */
    UINT16 phyId1;          /* phy Id 1 */
    UINT16 phyId2;          /* phy ID 2 */
    UINT32 retVal;          /* return value */
    UINT32 phyOui = 0;      /* PHY's manufacture ID */
    UINT32 phyMode;         /* PHY mode number */

    /* Intel Pro1000T adaptor uses Alaska transceiver */

    /* read device ID to check Alaska chip available */
    MII_READ (phyAddr, MII_PHY_ID1_REG, &phyId1, retVal);

    MII_READ (phyAddr, MII_PHY_ID2_REG, &phyId2, retVal);

    phyOui =  phyId1 << 6 | phyId2 >> 10;

    phyMode = (phyId2 & MII_ID2_MODE_MASK) >> 4;

    if (phyOui == MARVELL_OUI_ID && (phyMode == MARVELL_ALASKA_88E1000 ||
                                     phyMode == MARVELL_ALASKA_88E1000S))
        {
         /* This is actually a Marvell Alaska 1000T transceiver */

         /* disable PHY's interrupt */
         MII_READ (phyAddr, ALASKA_INT_ENABLE_REG, &regVal, retVal);
         regVal = 0;
         MII_WRITE (phyAddr, ALASKA_INT_ENABLE_REG, regVal, retVal);

         /* CRS assert on transmit */
         MII_READ (phyAddr, ALASKA_PHY_SPEC_CTRL_REG, &regVal, retVal);
         regVal |= ALASKA_PSCR_ASSERT_CRS_ON_TX;
         MII_WRITE (phyAddr, ALASKA_PHY_SPEC_CTRL_REG, regVal, retVal);

        /* set the clock rate when operate in 1000T mode */
         MII_READ (phyAddr, ALASKA_EXT_PHY_SPEC_CTRL_REG, &regVal, retVal);
         regVal |= ALASKA_EPSCR_TX_CLK_25;
         MII_WRITE (phyAddr, ALASKA_EXT_PHY_SPEC_CTRL_REG, regVal, retVal);
        }

    if (phyOui == INTEL_82544PHY_OUI_ID && (phyMode == INTEL_82544PHY_MODEL))
        {
         /* This is INTEL 82544GC/EI internal PHY */

         /* disable PHY's interrupt */
         MII_READ (phyAddr, INTEL_82544PHY_INT_ENABLE_REG, &regVal, retVal);
         regVal = 0;
         MII_WRITE (phyAddr, INTEL_82544PHY_INT_ENABLE_REG, regVal, retVal);

         /* CRS assert on transmit */
         MII_READ (phyAddr, INTEL_82544PHY_PHY_SPEC_CTRL_REG,
                   &regVal, retVal);
         regVal |= INTEL_82544PHY_PSCR_ASSERT_CRS_ON_TX;
         MII_WRITE (phyAddr, INTEL_82544PHY_PHY_SPEC_CTRL_REG,
                   regVal, retVal);

        /* set the TX_CLK rate when operate in 1000T mode */
         MII_READ (phyAddr, INTEL_82544PHY_EXT_PHY_SPEC_CTRL_REG,
                   &regVal, retVal);
         regVal |= INTEL_82544PHY_EPSCR_TX_CLK_25;
         MII_WRITE (phyAddr, INTEL_82544PHY_EXT_PHY_SPEC_CTRL_REG,
                   regVal, retVal);

        /* INTEL PHY's bug fixing ... */
        MII_WRITE (phyAddr, 29, 0x5, retVal);

        MII_READ (phyAddr, 30, &regVal, retVal);
        regVal |= 0x100;

        MII_WRITE (phyAddr, 30, regVal, retVal);
        }

     /* other PHYS .... */

     return;
     }

/*****************************************************************************
*
* sys543IntAck - acknowledge an 82543 interrupt
*
* This routine performs any 82543 interrupt acknowledge that may be
* required.  This typically involves an operation to some interrupt
* control hardware.
*
* This routine gets called from the 82543 driver's interrupt handler.
*
* This routine assumes that the PCI configuration information has already
* been setup.
*
* RETURNS: OK, or ERROR if the interrupt could not be acknowledged.
*/

LOCAL int sys543IntAck
    (
    int		unit		/* unit number */
    )
    {
    GEI_RESOURCE *pReso = &geiResources [unit];

    switch (pReso->boardType)
	{
	case PRO1000_543_BOARD:     /* handle PRO1000F LAN Adapter */
	case PRO1000_544_BOARD:     /* handle PRO1000F LAN Adapter */
	    break;

	default:
	    SYS_GEI_LOG ("sys543IntAck ERROR\n",0,0,0,0,0,0);
	    return (ERROR);
	}
    return (OK);
    }


/*****************************************************************************
*
* sys543IntEnable - enable 82543 interrupts
*
* This routine enables 82543 interrupts.  This may involve operations on
* interrupt control hardware.
*
* The 82543 driver calls this routine throughout normal operation to terminate
* critical sections of code.
*
* This routine assumes that the PCI configuration information has already
* been setup.
*
* RETURNS: OK, or ERROR if interrupts could not be enabled.
*/

LOCAL int sys543IntEnable
    (
    int		unit		/* unit number */
    )
    {
    GEI_RESOURCE *pReso = &geiResources [unit];

    switch (pReso->boardType)
	{
	case PRO1000_543_BOARD:     /* handle PRO1000F LAN Adapter */
	case PRO1000_544_BOARD:     /* handle PRO1000F LAN Adapter */
            intEnable (pReso->irq);
	    break;

	default:
	    SYS_GEI_LOG ("sys543IntEnable ERROR\n",0,0,0,0,0,0);
	    return (ERROR);
	}
    return (OK);
    }


/*****************************************************************************
*
* sys543IntDisable - disable 82543 interrupts
*
* This routine disables 82543 interrupts.  This may involve operations on
* interrupt control hardware.
*
* The 82543 driver calls this routine throughout normal operation to enter
* critical sections of code.
*
* This routine assumes that the PCI configuration information has already
* been setup.
*
* RETURNS: OK, or ERROR if interrupts could not be disabled.
*/

LOCAL STATUS sys543IntDisable
    (
    int    unit        /* unit number */
    )
    {
    GEI_RESOURCE *pReso = &geiResources [unit];

    switch (pReso->boardType)
	{
	case PRO1000_543_BOARD:        /* handle PRO1000F LAN Adapter */
	case PRO1000_544_BOARD:        /* handle PRO1000F LAN Adapter */
            intDisable (pReso->irq);
	    break;

	default:
	    SYS_GEI_LOG ("sys543IntDisable ERROR\n",0,0,0,0,0,0);
	    return (ERROR);
	}
    return (OK);
    }


/**************************************************************************
*
* sys543LocalToBus - convert local address to corresponding PCI address
*
* Converts a local bus (DRAM) address to the PCI address used by the NIC to
* access the local address.
*
* RETURNS: PCI bus address
*
*/

LOCAL UINT32  sys543LocalToBus
    (
    int unit,        /* unit number */
    UINT32 localAddr /* RP local address to convert */
    )

    {
    UINT32 sysAddr;

    sysAddr = localAddr + geiResources[unit].localToSysOffset;
    return (sysAddr);
    }

/**************************************************************************
*
* sys543BusToLocal - convert PCI address to corresponding local address
*
* Converts a PCI bus address in the IOP's memory window visible from the
* external bus to the corresponding local bus address.
*
* RETURNS: RP local address
*/

LOCAL UINT32  sys543BusToLocal
    (
    int unit,      /* unit number */
    UINT32 sysAddr /* PCI bus address to convert */
    )

    {
    UINT32 localAddr;

    localAddr = sysAddr - geiResources[unit].localToSysOffset;
    return (localAddr);
    }

/***************************************************************************
*
* sys543GeiInit - prepare LAN adapter for 8254x initialization
*
* This routine find out the PCI device, and map its memory and IO address.
* It must be done prior to initializing the 82557, sys557Init().  Also
* must be done prior to MMU initialization, usrMmuInit().
*
* RETURNS: N/A
*/

void sys543GeiInit (void)
{
    GEI_RESOURCE *pReso;  /* chip resources */
    UINT32 memBaseLow;    /* mem base low */
    UINT32 memBaseHigh;   /* mem base High */
    UINT32 flashBaseLow;  /* flash base low */
    UINT32 flashBaseHigh; /* flash base high */
    UINT32 ioBase;        /* io base */
    unsigned char irq;    /* irq number */
    unsigned int type;

    UINT i, unit, unitNum;

    for(i = 0; i < MAX_END_DEVS; ++i)
    {
      if(pendDevTbl[i].endLoadFunc == sysGei82543EndLoad)
        {
         pendDevTbl[i].processed = TRUE;
        }
    }

    /*
     * The following code tries to automatically detect
     * all instances of gei driver supported Ethernet cards.
     */

    for (unit = 0; unit < sysGeiUnits ; unit++)
    {

    pReso     = &geiResources [geiUnits];

    if(sysPciFindDevices(geiDevices, geiUnits, &pReso->pciBus, &pReso->pciDevice, &pReso->pciVendID, &pReso->pciDevID) != OK)
      {
        break;  /* found all instances */
      }

    switch(pReso->pciDevID) 
        {
        case PRO1000_544_PCI_DEVICE_ID_1:
        case PRO1000_544_PCI_DEVICE_ID_2:
        case PRO1000_544_PCI_DEVICE_ID_3:
            pReso->boardType = PRO1000_544_BOARD;     /* gei 82544's */
            break;

        case PRO1000_543_PCI_DEVICE_ID_1:
        case PRO1000_543_PCI_DEVICE_ID_2:
            pReso->boardType = PRO1000_543_BOARD;     /* gei 82543's */
            break;
        }

    pReso->pciFunc   = 0;

    /*
     *
     * 64-bit BARs
     *
     * Memory: BAR0: [31:17]: memory base
     *               [16:4] : read as "0"
     *               [3]    : 0 - device is not prefetchable
     *               [2:1]  : 10b - 64-bit address space
     *               [0]    : 0 - memory map decoded
     *
     *         BAR1: [63:32]: memory base, high bits
     *
     * FLASH : BAR2: if BAR0[31:xx]: flash memory base
     *                      [xx:4] : read as "0"
     *
     *                      where  64K 31:16 15:4
     *                            128K 31:17 16:4
     *                            256K 31:18 17:4
     *                            512K 31:19 18:4
     *
     *                      [3]    : 0 - device is not prefetchable
     *                      [2:1]  : 10b - 64-bit address space
     *                      [0]    : 0 - memory map decoded
     *
     *         BAR3: [63:32]: flash memory base, high bits
     *
     * IO    : BAR4: if BAR0[31:3]: memory base
     *                      [2:1] : 00b
     *                      [0]   : 1 - io map decoded
     *
     * 32-bit BARs
     *
     * Memory: BAR0: [31:17]: memory base, read/write
     *               [16:4] : read as "0"
     *               [3]    : 0 - device is not prefetchable
     *               [2:1]  : 00b - 32-bit address space
     *               [0]    : 0 - memory map decoded
     *
     * FLASH : BAR1: if BAR0[31:xx]: flash memory base
     *                      [xx:4] : read as "0"
     *
     *                      where  64K 31:16 15:4
     *                            128K 31:17 16:4
     *                            256K 31:18 17:4
     *                            512K 31:19 18:4
     *
     *                      [3]    : 0 - device is not prefetchable
     *                      [2:1]  : 00b - 32-bit address space
     *                      [0]    : 0 - memory map decoded
     *
     * IO    : BAR2: if BAR0[31:3]: memory base, read/write
     *                      [2:1] : 00b
     *                      [0]   : 1 - io map decoded
     *
     */

    /* read back memory base address and IO base address */
    pciConfigInLong (pReso->pciBus, pReso->pciDevice, pReso->pciFunc,
                     PCI_CFG_BASE_ADDRESS_0, &memBaseLow);

    type = memBaseLow & 0x6;
    pReso->addr64 = ((type & BAR0_64_BIT) == BAR0_64_BIT)? TRUE : FALSE;

    if (pReso->addr64)
        {
        pciConfigInLong (pReso->pciBus, pReso->pciDevice, pReso->pciFunc,
                         PCI_CFG_BASE_ADDRESS_1, &memBaseHigh);
        pciConfigInLong (pReso->pciBus, pReso->pciDevice, pReso->pciFunc,
                         PCI_CFG_BASE_ADDRESS_2, &flashBaseLow);
        pciConfigInLong (pReso->pciBus, pReso->pciDevice, pReso->pciFunc,
                         PCI_CFG_BASE_ADDRESS_3, &flashBaseHigh);
        pciConfigInLong (pReso->pciBus, pReso->pciDevice, pReso->pciFunc,
                         PCI_CFG_BASE_ADDRESS_4, &ioBase);
        }
    else
        {
        pciConfigInLong (pReso->pciBus, pReso->pciDevice, pReso->pciFunc,
                         PCI_CFG_BASE_ADDRESS_1, &flashBaseLow);
        ioBase = 0x0;
        memBaseHigh = 0x0;
        flashBaseHigh = 0x0;
       }

    pciConfigInByte (pReso->pciBus, pReso->pciDevice, pReso->pciFunc,
                     PCI_CFG_DEV_INT_LINE, &irq);

    pciConfigInWord (pReso->pciBus, pReso->pciDevice, pReso->pciFunc,
                     PCI_CFG_SUB_VENDER_ID, &pReso->subSysVendID);

    pciConfigInWord (pReso->pciBus, pReso->pciDevice, pReso->pciFunc,
                     PCI_CFG_SUB_SYSTEM_ID, &pReso->subSysDevID);

    pciConfigInByte (pReso->pciBus, pReso->pciDevice, pReso->pciFunc,
                     PCI_CFG_CLASS, &pReso->classCode);

    pciConfigInByte (pReso->pciBus, pReso->pciDevice, pReso->pciFunc,
                     PCI_CFG_SUBCLASS, &pReso->subClassCode);

    pciConfigInByte (pReso->pciBus, pReso->pciDevice, pReso->pciFunc,
                     PCI_CFG_PROGRAMMING_IF, &pReso->progIF);

    pciConfigInByte (pReso->pciBus, pReso->pciDevice, pReso->pciFunc,
                     PCI_CFG_REVISION, &pReso->revID);

    /* clear IO/Mem, mem type, prefetch bits */
    memBaseLow   &= ~0xf;
    flashBaseLow &= ~0xf;
    ioBase       &= ~0x7;

    /* over write the resource table with read value */

    pReso->memBaseLow    = memBaseLow + template_CPU_PCI_MEM0_BASE;
    pReso->memBaseHigh   = memBaseHigh;

    pReso->flashBaseLow  = flashBaseLow + template_CPU_PCI_MEM0_BASE;
    pReso->flashBaseHigh = flashBaseHigh;

    pReso->ioBase        = ioBase + template_CPU_PCI_IO_BASE;
    pReso->irq           = irq;