rominit.s

嵌入式操作系统VxWorks中板级支持包文件

 * COARSE_ENTRY addr,options
 * Virt addr 0x00000000 - 0x000fffff
 * Pointer to coarse page table t 0x8000.
 * (1 megabyte entry)
 */

COARSE_ENTRY 0x00008, 0x00000001

/*
 * PT_ENTRY base,x,ap,p,d,c,b,total
 * Virt addr 0x00100000 - 0x9fffffff
 * Read/write, non-cacheable, non-bufferable 
 * Covers ROM space, one megabyte and above 
 * (2558 1 megabyte entries) 
 */

PT_ENTRY 0x001,0,3,0,0,0,0,0x9ff

/*
 * PT_ENTRY base,x,ap,p,d,c,b,total
 * Virt addr 0xa0000000 - 0xfe7fffff 
 * Read/write, cacheable, bufferable, 
 * Covers all of RAM
 * (1512 1 megabyte entries) 
 */

PT_ENTRY 0xa00,0,3,0,0,1,1,0x5e8

/*
 * PT_ENTRY base,x,ap,p,d,c,b,total
 * Virt addr 0xfe800000 - 0xffffffff 
 * Read/write, non-cacheable, non-bufferable.
 * Covers 80321 MMRs, UART, CPLD, etc.
 * (24 1 megabyte entries)   
 */

PT_ENTRY 0xfe8,0,3,0,0,0,0,0x18 

/*******************************************************************************
*
* SECOND LEVEL TRANSLATION TABLE.
*
* This coarse second-level table contains 256 entries, each entry mapping
* 4k of memory (small page). Each entry occupies one 4-byte word, therefore
* the table length is 1 kilobyte.
*/

/* TODO - re-define according to template memory map */

/*
 * EX_ENTRY base,x,ap,c,b,total
 * Virt addr 0x00000000 - 0x00000fff
 * Physical address 0xa0000000
 * Read/write, cacheable, bufferable
 * Maps 4k of physical RAM down into
 * first 4k of virtual address space.
 */

EX_ENTRY 0xa0000,0,3,1,1,1

/*
 * EX_ENTRY base,x,ap,c,b,total
 * Virt addr 0x00001000 - 0x000fffff
 * Read/write, cacheable, bufferable.
 * Covers rest of first megabyte of ROM.
 */

EX_ENTRY 0x1,0,3,1,1,255


/* any data added here should be reflect in ROM_TEXT_BASE in Makefile as well as in config.h */

        .text
        .align 4

/*******************************************************************************
*
* romInit - entry point for VxWorks in ROM
*
* This is the start of the ROM code.  The CPU will vector here upon reset.
*
* romInit
*     (
*     int startType     /@ only used by 2nd entry point @/
*     )
*
* INTERNAL
* sysToMonitor examines the ROM for the first instruction and the string
* "Copy" in the third word so if this changes, sysToMonitor must be updated.
*
* Register r8 holds startType until jump to the code that starts the whole
* vxWorks boot process
*
*/

_ARM_FUNCTION(romInit)
_romInit:
cold:
        mov     r0, #BOOT_COLD   /* fall through to warm boot entry */

warm:
        b       bootStart

        /* copyright notice appears at beginning of ROM (in TEXT segment) */
        .ascii  "Copyright 2000 Wind River Systems, Inc. "
        .align 4

bootStart:
        mov     r8, r0                  /* store off startType */

/*** Disable Write Buffer Coalescing ***/
        mcr     p15, 0, r0, c7, c10, 4  /* Drain write/fill buffers */
        CPWAIT  (r0)                    /* wait for the write to happen */
        CPWAIT  (r0)                    /* wait for the write to happen */

        mrc     p15, 0, r0, c1, c0, 1   /* Read Auxiliary Control Reg */
        orr     r0, r0, #0x00000001     /* Disable Coalescing */
        mcr     p15, 0, r0, c1, c0, 1   /* Write Auxiliary Control Reg */
        CPWAIT  (r0)                    /* wait for the write to happen */

        DELAY   ( DELAY_2_MSECS, r6 )

/* Set core clock multiplier to x9, */
/* For CCLK=66MHz, frequency=600MHz */
        mov     r0, #0x07
        mcr     p14, 0, r0, c6, c0, 0
        CPWAIT  (r0)

/* Enable access to all Coprocessors */
        ldr     r0, =0x3fff
        mcr     p15, 0, r0, c15, c1, 0
        CPWAIT  (r0)                     /* Wait */

        mcr     p15, 0, r0, c7, c10, 4  /* Drain write/fill buffers */
        CPWAIT  (r0)                    /* wait for the write to happen */

/* Disable Interrupts */
        mrs     r1, cpsr                /* get current status */
        orr     r1, r1, #I_BIT | F_BIT  /* disable IRQ and FIQ */
        msr     cpsr, r1

/* Interrupts Disabled */
        ldr     r0, =template_MASK_ALL_INT
        mcr     p6, 0, r0, c0, c0, 0    /* Write Interrupt Control (INTCTL) Register */

/* Invalidate I-Cache, D-Cache, and BTB */
        mcr     p15, 0, r0, c7, c7, 0
        CPWAIT  (r0)                    /* Wait */

/* Drain Write/Fill buffer.  */
        mcr     p15, 0, r0, c7, c10, 4
        CPWAIT  (r0)


/*
 * TODO
 * Initial Peripheral Bus Unit devices here ...               
 */


/* fall through to warm boot entry */
        cmp     r8, #BOOT_COLD
        bne     warm_start

#ifdef INCLUDE_HEX_LED
#ifdef SECOND_HEX_LED
        HEX_DISPLAY_THIS ( r0, r1, (L7SEG_ALL_OFF), HEX_DISPLAY_MSB )
#endif
        HEX_DISPLAY_THIS ( r0, r1, (L7SEG_0 & L7SEG_Dot), HEX_DISPLAY_LSB )
#endif

#ifdef LOCAL_MEM_AUTOSIZE
/* DRAM sizing */
        bl      sdramSize               /* Figure out how much RAM */
#else
/*
 * Go with Factory default of 128M. Set up the registers for mcuInit.
 * mcuInit currently only uses r1 & r2...
 * r0 - SDRAM size in megabytes.
 * r1 - bank 0 size in megabytes.
 * r2 - bank 1 size in megabytes.
 * r3 - DIMM count (1 or 2).
 * r4 - SDRAM width in bits (8 or 16 bits).
 * r5 - SDRAM refresh rate type.
 */
        ldr     r0, =template_SDRAM_FIXED_SIZE
        ldr     r1, =template_SDRAM_BANK0_SIZE
        ldr     r2, =template_SDRAM_BANK1_SIZE
        ldr     r3, =template_SDRAM_DIMM_COUNT
        ldr     r4, =template_SDRAM_FIXED_WIDTH
        ldr     r5, =template_MCU_RFR_DEFAULT_VAL
#endif

        mov     r12, r0                 /* Save off SDRAM size for scrubbing */

/* Memory controller initialization */
        bl      mcuInit                 /* Set up memory controller */

#ifdef INCLUDE_HEX_LED
        HEX_DISPLAY_THIS ( r0, r1, (L7SEG_1 & L7SEG_Dot), HEX_DISPLAY_LSB )
#endif

/* flush instruction and data TLBs */
        mcr     p15, 0, r0, c8, c7, 0
        CPWAIT  (r0)                    /* Wait */

/* Enable Instruction Cache */
        mrc     p15, 0, r0, c1, c0, 0   /* Read Control Register*/
        orr     r0, r0, #0x1000         /* Set I-Cache bit */
        mcr     p15, 0, r0, c1, c0, 0   /* Write Back Control Register */
        CPWAIT  (r0)                    /* Wait */

#ifdef INCLUDE_HEX_LED
        HEX_DISPLAY_THIS ( r0, r1, (L7SEG_2 & L7SEG_Dot), HEX_DISPLAY_LSB )
#endif

/*** MMU Setup ***/
/* Set Translation Table Base */
        ldr     r0, =MMU_TRANSLATION_BASE
        mcr     p15, 0, r0, c2, c0, 0   /* Set Translation Table Base Register */
        CPWAIT  (r0)                    /* Wait */

/* Invalidate Instruction, Data TLBs */
        mcr     p15, 0, r0, c8, c7, 0   /* Flush I & D TLBs*/
        CPWAIT  (r0)                    /* Wait */

/* Set Domain Access Control Register */
        ldr     r0, =0xffffffff         /* Set All 16 domains to manager access */
        mcr     p15, 0, r0, c3, c0, 0   /* Set Domain Permissions */
        CPWAIT  (r0)                    /* Wait */

/* Enable MMU */
        mrc     p15, 0, r0, c1, c0, 0   /* Read Control Register */
        orr     r0, r0, #0x00000001     /* Enable MMU */

        mcr     p15, 0, r0, c1, c0, 0   /* Write Back the Control Register */
        CPWAIT  (r0)                    /* Wait */

#ifdef INCLUDE_HEX_LED
        HEX_DISPLAY_THIS ( r0, r1, (L7SEG_3 & L7SEG_Dot), HEX_DISPLAY_LSB )
#endif

/*** Data Cache Setup ***/
/* Drain Write/Fill Buffers */
        mcr     p15, 0, r0, c7, c10, 4  /* Drain */
        CPWAIT  (r0)                    /* Wait */

/* Enable Data Cache */
        mrc     p15, 0, r0, c1, c0, 0   /* Read Control Reg */
        orr     r0, r0, #0x00000004     /* Enable Data Cache */
        mcr     p15, 0, r0, c1, c0, 0   /* Write Back */
        CPWAIT  (r0)                    /* Wait */

/* Enable Branch Target Buffer */
        mrc     p15, 0, r0, c1, c0, 0   /* Read Control Reg */
        orr     r0, r0, #0x00000800     /* Enable BTB */
        mcr     p15, 0, r0, c1, c0, 0   /* Write Back the Control Reg */
        CPWAIT  (r0)                    /* Wait */

#ifdef INCLUDE_HEX_LED
        HEX_DISPLAY_THIS ( r0, r1, (L7SEG_4 & L7SEG_Dot), HEX_DISPLAY_LSB )
#endif

/* Scrubbing Memory */
        ldr     r11, =template_SDRAM_BASE_ADDR  /* base address of SDRAM */
        mov     r10, r12                       /* save size of the memory */

        mov     r0, #0x00000000
        mov     r1, #0x00000000
        mov     r2, #0x00000000
        mov     r3, #0x00000000
        mov     r4, #0x00000000
        mov     r5, #0x00000000
        mov     r6, #0x00000000
        mov     r7, #0x00000000

ScrubNext32Bytes:
        stmia   r11!, {r0-r7}           /* Write 64-bit wide data */
        subs    r12, r12, #0x00000020
        bne     ScrubNext32Bytes        /* Write Next 32 bytes */

ScrubDone:

#ifdef INCLUDE_HEX_LED
        HEX_DISPLAY_THIS ( r0, r1, (L7SEG_5 & L7SEG_Dot), HEX_DISPLAY_LSB )
#endif

/* Clean (Write Back) the Data Cache by Allocating non-existent memory address tags
 * for the cache line. Since tags are mapped into a non-existen memory address, it is
 * guaranteed that all cache lines will be cleaned
 */
        ldr     r1, =LOCAL_MEM_LOCAL_ADRS  /* use a CACHEABLE area of */
        add     r1, r1, r10             /* add in DRAM_SIZE */
        mov     r0, #SZ_1K              /* the memory map above SDRAM */

AllocNextDCacheLine:
        mcr     p15, 0, r1, c7, c2, 5   /* Allocate a DCache Line */
        add     r1, r1, #SZ_32          /* increment the address to the next cache line */
        subs    r0, r0, #1              /* decrement the loop count */
        bne     AllocNextDCacheLine

/* Merged into one loop */
/* DRAM_BASE + DRAM_SIZE + DCACHE_SIZE */
        ldr     r2, =(LOCAL_MEM_LOCAL_ADRS+SZ_32K)   /* DRAM_BASE + DCACHE_SIZE */
        add     r2, r2, r10             /* add in DRAM_SIZE */
        mov     r0, #SZ_64

AllocNextMiniDCacheLine:
        mcr     p15, 0, r2, c7, c2, 5   /* setup dcache */
        add     r2, r2, #SZ_32          /* increment address by 32 */
        subs    r0, r0, #1              /* decrement the loop */
        bne     AllocNextMiniDCacheLine /* continue */

/* Invalidate Whole Data Cache */
        mcr     p15, 0, r0, c7, c6, 0
        CPWAIT  (r0)

/* Drain Write/Fill buffer.  */
        mcr     p15, 0, r0, c7, c10, 4
        CPWAIT  (r0)

#ifdef INCLUDE_HEX_LED
        HEX_DISPLAY_THIS ( r0, r1, (L7SEG_6 & L7SEG_Dot), HEX_DISPLAY_LSB )
#endif

        b       vxWorks_boot

warm_start:
/* flush instruction and data TLBs */
        mcr     p15, 0, r0, c8, c7, 0
        CPWAIT  (r0)                    /* Wait */

/* Enable Instruction Cache */
        mrc     p15, 0, r0, c1, c0, 0   /* Read Control Register*/
        orr     r0, r0, #0x1000         /* Set I-Cache bit */
        mcr     p15, 0, r0, c1, c0, 0   /* Write Back Control Register */
        CPWAIT  (r0)                    /* Wait */

/* Set Translation Table Base */
        ldr     r0, =MMU_TRANSLATION_BASE
        mcr     p15, 0, r0, c2, c0, 0   /* Set Translation Table Base Register */
        CPWAIT  (r0)                    /* Wait */

/* Invalidate Instruction, Data TLBs */
        mcr     p15, 0, r0, c8, c7, 0   /* Flush I & D TLBs*/
        CPWAIT  (r0)                    /* Wait */

/* Set Domain Access Control Register */
        ldr     r0, =0xffffffff         /* Set All 16 domains to manager access */
        mcr     p15, 0, r0, c3, c0, 0   /* Set Domain Permissions */
        CPWAIT  (r0)                    /* Wait */

/* Enable MMU */
        mrc     p15, 0, r0, c1, c0, 0   /* Read Control Register */
        orr     r0, r0, #0x00000001     /* Enable MMU */

        mcr     p15, 0, r0, c1, c0, 0   /* Write Back the Control Register */
        CPWAIT  (r0)                    /* Wait */

/* Drain Write/Fill Buffers */
        mcr     p15, 0, r0, c7, c10, 4  /* Drain */
        CPWAIT  (r0)                    /* Wait */

/* Enable Data Cache */
        mrc     p15, 0, r0, c1, c0, 0   /* Read Control Reg */
        orr     r0, r0, #0x00000004     /* Enable Data Cache */
        mcr     p15, 0, r0, c1, c0, 0   /* Write Back */
        CPWAIT  (r0)                    /* Wait */

/* Enable Branch Target Buffer */
        mrc     p15, 0, r0, c1, c0, 0   /* Read Control Reg */
        orr     r0, r0, #0x00000800     /* Enable BTB */
        mcr     p15, 0, r0, c1, c0, 0   /* Write Back the Control Reg */
        CPWAIT  (r0)                    /* Wait */

vxWorks_boot:

/*  Now jump to the code that starts the whole vxWorks boot process */
        mov     r0, r8
        ldr     sp, L$STACK_ADDR
        ldr     pc, L$StrtInRam

/************************** HEX LED Helpers ***********************************/

#ifdef INCLUDE_HEX_LED
SevenSegDisplay:
#ifdef SECOND_HEX_LED
        ldr             r2, =template_7SEG_LED_MSB_REG
        strb            r1, [r2]
#endif

        ldr             r2, =template_7SEG_LED_LSB_REG
        strb            r0, [r2]

        mov             pc, lr
#endif

/*******************************************************************************
* mcuInit - set up the memory controller
*
* PARAMETERS
*
* r0 - SDRAM size in megabytes.
* r1 - bank 0 size in megabytes.
* r2 - bank 1 size in megabytes.
* r3 - DIMM count (1 or 2).
* r4 - SDRAM width in bits (8 or 16 bits).
* r5 - SDRAM refresh rate type.
*
* RETURNS:
*
*/

mcuInit:

        /* TODO - Consult template Spec to determine how to initialize Memory Controller */

        mov     pc, lr

#ifdef LOCAL_MEM_AUTOSIZE
/*******************************************************************************
* sdramSize - determine the size of the installed SDRAM
*
* This routine should read Serial Presence Detect (SPD) data from the EEPROM fitted
* to an SDRAM DIMM, in order to determine the DIMM's size. The EEPROM is
* accessed using the templates I2C bus interface unit.
*
* Data held within the EEPROM should conform with the JEDEC SDRAM SPD
* specification and, more specifically, the PC100 / PC133 SDRAM SPD
* specification defined by Intel and others. For details on these
* specifications, see JEDEC's web site at http://www.jedec.org, and Intel's
* developer site (memory techologies section) at http://developer.intel.com.
*
* This routine should halt and display an error code on the board's LED if any
* of the following conditions are detected:
*
* - No SDRAM banks found.
* - More than two SDRAM banks found.
*
* SEE ALSO
*
* JEDEC web site, http://www.jedec.org
* Intel Developer web site, http://developer.intel.com
* Intel 80321 Specification
*
* NOTE
*
* ASSUMPTIONS
*
* This code typically makes the following assumptions:
*
* If only one SDRAM bank is populated, it is bank 0.
* If two banks, both are assumed to be of the same size.
* All DIMMs attached to the system use the same SDRAM width (x8 or x16).
*
* PARAMETERS
*
* None.
*
* RETURNS:
*
* r0 - SDRAM size in megabytes.
* r1 - bank 0 size in megabytes.
* r2 - bank 1 size in megabytes.
* r3 - DIMM bank count (1 or 2).
* r4 - SDRAM width in bits (8 or 16 bits).
* r5 - SDRAM refresh rate type.
*
*/

sdramSize:

        /* TODO - Query SDRAM DIMM's EPROM to determine SDRAM parameters */

        mov     pc, lr
#endif

L$StrtInRam:	.long	ROM_TEXT_ADRS + FUNC(romStart) - FUNC(romInit)
L$STACK_ADDR:	.long	STACK_ADRS