config.h

嵌入式操作系统VxWorks中板级支持包文件

 #define DEFAULT_BOOT_LINE BOOT_DEV_NAME \
          "(0,0)host:/usr/wpwr/target/config/template/vxWorks " \
          "h=90.0.0.30 e=90.0.0.50 u=username tn=targetname"

/*
 * User application initialization
 *
 * USER_APPL_INIT must be a valid C statement or block.  It is
 * included in the usrRoot() routine only if INCLUDE_USER_APPL is
 * defined.  The code for USER_APPL_INIT is only an example.  The
 * user is expected to change it as needed.  The use of taskSpawn
 * is recommended over direct execution of the user routine.
 */

#undef  INCLUDE_USER_APPL
#define USER_APPL_INIT \
        { \
        IMPORT int myAppInit(); \
        taskSpawn ("myApp", 30, 0, 5120, \
                   myAppInit, 0x1, 0x2, 0x3, 0,0,0,0,0,0,0); \
        }

/*!!! In most situations it is not necessary to change the following macros !!!*/

/* TODO - add support for either LED/HEX display capabilities... */

/*** USER LEDs ***/
#undef INCLUDE_USER_LED

/*** Hex LEDs ***/
#undef INCLUDE_HEX_LED
#ifdef INCLUDE_HEX_LED
 #define SECOND_HEX_LED 
#endif

/*** UART ***/
/* Serial port configuration */

 #define INCLUDE_SERIAL
 #ifdef INCLUDE_SERIAL
/*
 * If there are two UARTs. The default UART defs like NUM_TTY, CONSOLE_TTY
 * and CONSOLE_BAUD_RATE in configAll.h should work fine. If you change any
 * defaults, it might affect the WDB defs also, so cross check with WDB defs.
 *
*/
 #define N_UARTS              1  /* using UART 1 for debug */
 #undef  SECOND_UART             /* define if 2nd UART exists */

 #undef  NUM_TTY
 #define NUM_TTY              N_UARTS

 #define DEFAULT_BAUD         9600  
 #define UART_DEFAULT_BAUD    9600  

 #undef  CONSOLE_TTY
 #define CONSOLE_TTY          0

 #undef  CONSOLE_BAUD_RATE
 #define CONSOLE_BAUD_RATE    DEFAULT_BAUD

/*** WDB ***/
/*
 * Define SERIAL_DEBUG to enable debugging
 * via the serial ports
 */
 #undef SERIAL_DEBUG
 #ifdef SERIAL_DEBUG
  #define WDB_NO_BAUD_AUTO_CONFIG

  #undef WDB_COMM_TYPE
  #undef WDB_TTY_BAUD
  #undef WDB_TTY_CHANNEL
  #undef WDB_TTY_DEV_NAME

  #define WDB_COMM_TYPE       WDB_COMM_SERIAL /* WDB in Serial mode */
#ifdef SECOND_UART
  #define WDB_TTY_BAUD        9600            /* Baud rate for WDB Connection */
  #define WDB_TTY_CHANNEL     1               /* COM PORT #2 */
  #define WDB_TTY_DEV_NAME    "/tyCo/1"       /* default TYCODRV_5_2 device name */
#else
  #define WDB_TTY_BAUD        DEFAULT_BAUD    /* Baud rate for WDB Connection */
  #define WDB_TTY_CHANNEL     0               /* COM PORT #1 */
  #define WDB_TTY_DEV_NAME    "/tyCo/0"       /* default TYCODRV_5_2 device name */
#endif
 #endif /* SERIAL_DEBUG */
 #endif /* INCLUDE_SERIAL */

/* cache support */

/*
 * Cache configuration
 *
 * TODO -
 * All cache is turned off to begin with. Activate caching after basic
 * BSP functionality is achieved.  Start with instruction caching, followed
 * by data caching.  Begin without snooping options; and turn those on
 * later if the board supports it.
 *
 * Note that when MMU is enabled, cache modes are controlled by
 * the MMU table entries in sysPhysMemDesc[], not the cache mode
 * macros defined here.
 */

 #undef INCLUDE_CACHE_SUPPORT

 #undef USER_I_CACHE_ENABLE
 #undef  USER_I_CACHE_MODE
 #define USER_I_CACHE_MODE       CACHE_DISABLED

 #undef USER_D_CACHE_ENABLE
 #undef  USER_D_CACHE_MODE
 #define USER_D_CACHE_MODE       CACHE_DISABLED

 #undef  USER_B_CACHE_ENABLE

/*** MMU ***/
/*
 * Initial MMU translation tabel location. Make sure it is 16K aligned.
 * ROM_TEXT_ADRS should also be recalculted, if this MMU_TRANSLATION_BASE is
 * changed.
 */
  #undef INCLUDE_MMU_BASIC
  #undef INCLUDE_MMU_FULL

 #define MMU_TABLE_SIZE       0x8800

 #define MMU_TRANSLATION_BASE 0x00004000 /* translation tabel location */
 #define MMU_TABLE_END        MMU_TABLE_BASE_ROM+MMU_TABLE_SIZE

 #if defined(INCLUDE_MMU_BASIC) || defined(INCLUDE_MMU_FULL)
  #define INCLUDE_MMU
 #endif

 #undef VM_PAGE_SIZE
 #define VM_PAGE_SIZE         4096

/* Memory configuration */
 #undef  LOCAL_MEM_AUTOSIZE                /* run-time memory sizing */
 #define LOCAL_MEM_LOCAL_ADRS 0xA0000000   /* 0xA0000000 */
 #define LOCAL_MEM_SIZE       0x08000000   /* Currently limited to Max of 128 Meg */
 #define LOCAL_MEM_RESERVED   0x00000000   /* 0x0 */

/*** RAM Information ***/

/*
 * The constants ROM_TEXT_ADRS, ROM_SIZE, RAM_HIGH_ADRS, and RAM_LOW_ADRS
 * are defined in config.h and Makefile.
 * All definitions for these constants must be identical.
 *
 * TODO - Make sure these values match those in your Makefile.  The values
 * shown below are the defaults for a 68000 series system.  Pay particular
 * attention to ROM_TEXT_ADRS and ROM_WARM_ADRS.  The correct default values
 * are in the Makefile for each template BSP.
 */

/* RAM starting address, RAM Size */
 #define RAM_LOW_ADRS         0xA0010000

/* Link Address: To where the image will be decompressed */
 #define RAM_HIGH_ADRS        0xA0200000

 #define SDRAM_VIRT_OFFSET    (LOCAL_MEM_LOCAL_ADRS + LOCAL_MEM_RESERVED)

/*** ROM Information ***/
/*
 * Boot ROM is an image written into Flash ROM and started
 * by the template Primary Boot Loader.
 *
 * The following parameters are defined here and in the Makefile.
 * They must be kept synchronized; effectively config.h depends on
 * Makefile. Any changes made here must be made in the Makefile and vice
 * versa.
 *
 * ROM_BASE_ADRS is the base of the Flash ROM
 * ROM_TEXT_ADRS is the entry point of the VxWorks image
 * ROM_SIZE is the size of the part of the Flash ROM allocated to the VxWorks
 *          image (block size - size of headers)
 *
 * Two other constants are used:
 * ROM_COPY_SIZE is the size of the part of the ROM to be copied into RAM
 *               (uncompressed bootrom)
 * ROM_SIZE_TOTAL is the size of the entire Flash ROM (used in sysPhysMemDesc)
 *
 * The address of the Flash block being used is:
 *    ROM_BASE_ADRS + (block << 18)   (blocks are ROM_SIZE)
 * The boot ROM image is at an offset of 0xC0 into this block - 0x40
 * bytes for a Flash header, 0x80 bytes for an AIF header
 *
 * The values are given as literals here to make it easier to ensure
 * that they are the same as those in the Makefile.
 */
 #define ROM_BASE_ADRS	      0x00000000 /* Blank 1 for booting */

/*
 * Where the text starts in ROM, (address of _romInit)...
 */
 #define ROM_TEXT_ADRS	      MMU_TRANSLATION_BASE + 0x00004400

/*
 * The size must be big enough so that
 *    (ROM_BASE_ADRS + ROM_SIZE - ROM_TEXT_ADRS) >= size of boot image
 * We allow up to an arbitrary 128K for the image.
 */
 #define ROM_SIZE             0x00400000      /* 4MB size of flash ROM */
 #if (ROM_BASE_ADRS + ROM_SIZE - ROM_TEXT_ADRS) < 0x20000
  #error  ROM_ values need checking in config.h/Makefile
 #endif

/*
 * ISR_STACK_SIZE is defined here rather than in ../all/configAll.h (as is
 * more usual) because the stack size depends on the interrupt structure of the
 * BSP.
 */
 #define ISR_STACK_SIZE	      0x1000   /* ISR Stack Size 4K */

 #undef STACK_SAVE
 #define STACK_SAVE           512      /* maximum stack used to preserve */

/*
 * make use of data cache for fast DRAM
 */
 #undef INCLUDE_FAST_DRAM
 #ifdef INCLUDE_FAST_DRAM
  #define FD_CACHELINE        8             /* 8 UINT32's in a cache line (32-bytes) */
  #define FD_LINESPERSET      28            /* 28 available cache lines per set */
  #define FD_SETS             32            /* 32 sets in data cache */

  #define FD_MAX_LINES (FD_LINESPERSET * FD_SETS) /* Max number of lines one can allocate (28 x 32) */

  #define FD_ORIGIN           0xdeadbeef    /* location of virtual address */
  #define FD_MAX_SIZE         0x7000        /* Max size for MMU table description, 28Kbytes */

/* modify based on the number of cache lines you want to use as data ram... */
  #define FD_NUMLINES         FD_MAX_LINES  /* set for max 28Kbytes */
 #endif

 #include "template.h"           /* Verify user options, specify i/o addr etc (board specific) */

/*
 * Enable Flash as NvRam. Use the last 512 bytes of flash bank 1
 */
 #undef INCLUDE_FLASH
 #ifdef INCLUDE_FLASH
  #define SYS_FLASH_TYPE        FLASH_28F640J3A   /* Specify 28F640J3A 16-bit, 8M part */
  #define FLASH_WIDTH	        2
  #define FLASH_CHIP_WIDTH      2
  #define FLASH_WIDTH_SPECIAL_2
  #define FLASH_SEGMENT_SIZE    0x20000		  /* sector size of 28F640 */
  #define FLASH_ADRS	        ((IQ80321_BOOT_FLASH_ADDR + IQ80321_BOOT_FLASH_SIZE) \
                                 - FLASH_SEGMENT_SIZE)
  #define FLASH_SIZE	        FLASH_SEGMENT_SIZE
  #define NV_RAM_SIZE	        FLASH_SEGMENT_SIZE
  #undef NV_BOOT_OFFSET
  #define NV_BOOT_OFFSET        FLASH_SEGMENT_SIZE - 0x200
  #undef FLASH_NO_OVERLAY
 #else
  #define NV_RAM_SIZE	      NONE
 #endif /* INCLUDE_FLASH */

#ifdef __cplusplus
}
#endif

#endif  /* INCconfigh */

#if defined(PRJ_BUILD)
 #include "prjParams.h"
#endif