config.h

嵌入式操作系统VxWorks中板级支持包文件

/* config.h - template configuration header file */

/* Copyright 2002 Wind River Systems, Inc. */

/*
TODO -  Remove the template modification history and begin a new history
        starting with version 01a and growing the history upward with
        each revision.

modification history
--------------------
01b,28may02,scm remove actual reference to iq80321...
01a,21may02,scm written
*/

/*
This file contains the configuration parameters for the template BSP.
This template starts simple - with most facilities excluded by default.

TODO -
Present the user with simple straight forward options.  Do not ask the
user to encode values together to form a value to be loaded in a register.
Let the source code, or the pre-processor, do the computational work to
determine what value to load in a particular register.

Fill in this file with I/O addresses and related constants for the
template BSP. Anything with "template" as a prefix needs to examined 
and re-named to id the BSP (i.e. iq80321, iq80310, etc.) 

*/

#ifndef INCconfigh
 #define INCconfigh

#ifdef __cplusplus
extern "C" {
#endif

/** BSP version/revision identification, before configAll.h **/

 #define BSP_VER_1_1          1      /* BSP Version */
 #define BSP_VERSION          "1.0"  /* Version string */
 #define BSP_REV              "/0"   /* 0 for first revision */

 #include "configAll.h"	/* Include the default configurations */

/* TODO - values in this header file are dummy values, update as needed */

/** Selection Macros, which might have affect later **/

 #undef INCLUDE_SYS_HW_INIT_0
 #ifdef INCLUDE_SYS_HW_INIT_0
  #ifndef _ASMLANGUAGE
   IMPORT void sysHwInit0 (void);
  #endif
  #define SYS_HW_INIT_0() sysHwInit0 ()
 #endif

 #undef INCLUDE_AUX_CLK 
 #ifdef INCLUDE_AUX_CLK 
 #define AUX_CLK_AVAIL        TRUE 
 #endif

 #undef INCLUDE_TIMESTAMP
 #ifdef INCLUDE_TIMESTAMP
 #define INCLUDE_USER_TIMESTAMP

 #ifdef INCLUDE_USER_TIMESTAMP
  #define USER_TIMESTAMP      sysTimestamp
  #define USER_TIMESTAMPLOCK  sysTimestampLock
  #define USER_TIMEENABLE     sysTimestampEnable
  #define USER_TIMEDISABLE    sysTimestampDisable
  #define USER_TIMECONNECT    sysTimestampConnect
  #define USER_TIMEPERIOD     sysTimestampPeriod
  #define USER_TIMEFREQ       sysTimestampFreq
 #endif  /* INCLUDE_USER_TIMESTAMP */
 #endif

 #define INCLUDE_EXC_HANDLING
 #define INCLUDE_EXC_TASK

 #define INCLUDE_RAM_PAGE_TABLE

 #define INCLUDE_SHOW_ROUTINES 

/*
 * defined to work with standalone image and visionClick/Probe
 * if defined, then define STANDALONE_NET, and undefine INCLUDE_FLASH...
 * also flush out DEFAULT_BOOT_LINE for IPs and target name...
 *
 * under visionClick/Probe you must convert your vxWorks.st into a "bdx" image...
 *
 * convert.exe "Z:\wpwr\target\config\ibrh80200\vxWorks.st" -c -m gnu -b -z
 *
 * under visionClick/Probe select from menu bar: " TOOLS/CONVERT OBJECT MODULES",
 * and :
 *   (1) add path to vxWorks.st image,
 *   (2) check "create symbol file for visionClick"
 *   (3) check "create bdx file for RAM download"
 *
 */
 #undef INCLUDE_HSI_PROBE    /* work with standalone image and probe */

/*
 * STANDALONE_NET must be defined for network debug with
 * standalone vxWorks
 */
 #undef STANDALONE_NET

/* PCI configuration */
 #undef INCLUDE_PCI
 #ifdef INCLUDE_PCI
  #undef INCLUDE_PCI_AUTOCONF             /* No auto for GEI 544 */
  #undef PCI_AUTO_DEBUG

  #define INCLUDE_END

/*
 * TODO -
 * Only those options that are actually user changeable should be defined
 * here.  Options that cannot be changed should be moved to template.h.
 */

  /*-------------------------------------------------------------
   * IQ80321 PCI Variables...
   * ------------------------------------------------------------*/

  /* IQ80321 CPU to PCI Bridge Device ID */
  #define IQ80321_CPU_PCI_DEVID             0xdeadbeef

  /* Max number of END devices  - set to same as number of PCI slots */
  #define IQ80321_MAX_END_DEVS              3

  /* PCI Interface Base Address */
  #define IQ80321_CPU_PCI_BASE              0x80000000

  #define IQ80321_CPU_PCI_MEM0_BASE         IQ80321_CPU_PCI_BASE
  #define IQ80321_CPU_PCI_MEM1_BASE         (IQ80321_CPU_PCI_BASE + SZ_64M)

  #define IQ80321_CPU_PCI_IO_BASE           0x90000000
  #define IQ80321_CPU_PCI_IO16_BASE         0x90008000

  /* All PCI Space Begins at 0 */
  #ifdef SECONDARY_SLOT_GEI_543
   #define IQ80321_PCI_BASE                 0x00100000 /* Errata prevents 0 based PCI */
  #else
   #define IQ80321_PCI_BASE                 0x00000000 /* PCI Space Address */
  #endif

  #define IQ80321_PCI_MEM0_BASE             (IQ80321_PCI_BASE + 0x00000000)
  #define IQ80321_PCI_MEM1_BASE             (IQ80321_PCI_BASE + SZ_64M)

  #define IQ80321_PCI_IO_BASE               (IQ80321_PCI_BASE + 0x00000000)
  #define IQ80321_PCI_IO16_BASE             (IQ80321_PCI_BASE + SZ_32K)

  #define IQ80321_PCI_CONFIG_ADDR           IQ80321_OCCAR_REG
  #define IQ80321_PCI_CONFIG_DATA           IQ80321_OCCDR_REG

  /* PCI (non-prefetchable) memory address to CPU address */
  #define PCI_MEMIO2LOCAL(x)                ((x) + IQ80321_CPU_PCI_BASE)

  /* PCI IO memory address to CPU address */
  #define PCI_IO2LOCAL(x)                   ((x) + IQ80321_CPU_PCI_IO_BASE)

  /*
   * Cache Line Size - in number of 32-bit words
   * It might be thought that we would set this to (_CACHE_ALIGN_SIZE/4), but,
   * in fact, the areas of memory mapped for use either by PCI I/O and
   * PCI Configuration  and the area of (ARM) memory used by the Ethernet
   * controller are marked as non-cacheable, so we should set it to zero.
   */
  #define PCI_CLINE_SZ                      32

  /*
   * Latency Timer value
   * A sensible value for this depends what we are using PCI for.
   * (Rather arbitrarily) leave it at 0 (the reset default value)
   */
  #define PCI_LAT_TIMER                     0x0

  /* For manual configuration of END devices on PCI */
  #define PCI_MAX_DEV                       32
  #define PCI_MAX_BUS                       2
  #define PCI_IO_ADR                        0
  #define PCI_MEM_ADR                       0
  #define PCI_INT_LVL                       0
  #define PCI_INT_VEC                       0
  #define PCI_MAX_END_DEV                   4

  #define PCICFG_BAR_0                      0x10
  #define PCICFG_BAR_1                      0x14
  #define PCICFG_BAR_2                      0x18
  #define PCICFG_SUBSYSTEM_ID               0x2e
  #define PCICFG_INT_PIN                    0x3d

  /* unknown or unsupported board type */
  #define BOARD_TYPE_UNKNOWN                (-1)

  #define DEFAULT_PAGE_SIZE                 0x0001000

  #define DEFAULT_MEMORY_ALIGNMENT          0x1000
  #define DEFAULT_IO_ALIGNMENT              0x800

  /*
   * Dummy interrupt number for pciIntConnect(): must be passed a real
   * interrupt vector number. This allows for non-linear mappings
   * between interrupts, slots etc.
   */
  #define INT_NUM_IRQ0                      0

/*
 * TODO -
 * Determine type of END driver supported. 
 * Options that cannot be changed should be moved to template.h.
 */

  #undef INCLUDE_FEI_END                /* include FEI END Ethernet driver, for debug purposes... */
  #ifdef  INCLUDE_FEI_END
    #define SYS_FEI_UNITS     1          /* max units supported */
    #define I82559ERMAC  { 0x00, 0xD0, 0xDE, 0xAD, 0xBE, 0xEF }
  #endif /* INCLUDE_FEI_END */

  #undef INCLUDE_GEI_END                /* include GEI END Ethernet driver */
  #ifdef INCLUDE_GEI_END
   #undef SECONDARY_SLOT_GEI_543         /* running 82543 off of PCI Secondary Slot?, need errata workaround */

   #define INCLUDE_ANSI_ALL
   #define INCLUDE_FLOATING_POINT        /* floating point output for netperf */

   /*
    * The number of 82543 interfaces to attempt to start on this board.
    * Adjust SYS_GEI_UNITS as desired. Make sure that IP_MAX_UNITS is
    * at least this big.
    */
   #ifdef  INCLUDE_FEI_END
    #define SYS_GEI_UNITS     1   
    #define MAX_END_DEVS      SYS_GEI_UNITS + SYS_FEI_UNITS /* this MUST equal the actual size(-1) of endDevTbl */
   #else
    #define SYS_GEI_UNITS     2
    #define MAX_END_DEVS      SYS_GEI_UNITS /* this MUST equal the actual size(-1) of endDevTbl */
   #endif

   #if IP_MAX_UNITS < SYS_GEI_UNITS
    #undef IP_MAX_UNITS
    #define IP_MAX_UNITS SYS_GEI_UNITS
   #endif

   #define GEI_RXDES_NUM      0x100
   #define GEI_TXDES_NUM      0x100

   #define GEI_USR_FLAG       0

   #define GEI_IP_ADDR        "90.0.0.10"
   #define GEI_HOST_NAME      "hostname"
   #define GEI_SUBNET_MASK    0xffffff00
  #endif     /* INCLUDE_GEI_END */

  #undef WDB_COMM_TYPE
  #define WDB_COMM_TYPE       WDB_COMM_END

  #define INCLUDE_PING

  #define INCLUDE_NET_SHOW

 #endif  /* INCLUDE_PCI */

 #ifdef INCLUDE_FEI_END  /* for now if FEI used default to it for boot, due to bad onboard GEI port */ 
   #define BOOT_DEV_NAME      "fei"
 #else
   #define BOOT_DEV_NAME      "gei"
 #endif