sysend.c

vxworks的BSP开发配置文件

IMPORT FUNCPTR  feiEndIntConnect;
IMPORT FUNCPTR  feiEndIntDisconnect;
IMPORT END_OBJ* fei82557EndLoad (char *, void *);
IMPORT void	sysFlashBoardDelay (void);
extern void sysDelay(void);

/* forward declarations */

LOCAL UINT16    sys557eepromRead (int unit, int location);
LOCAL UINT32    sys557mdioRead   (int unit, int phyId, int location);
LOCAL UINT32    sys557mdioWrite  (int unit, int phyId, int location, int value);
LOCAL int       sys557IntEnable  (int unit);
LOCAL int       sys557IntDisable (int unit);
LOCAL int       sys557IntAck     (int unit);
UINT32 sys557EndPhysToPci ( int	unit, UINT32 PhysAddr);
UINT32 sys557EndPciToPhys ( int	unit, UINT32 PhysAddr);

#endif /* INCLUDE_FEI82557END */

/*******************************************************************************
*
* sysLanPciInit - prepare LAN adapter for initialization
*
* This routine find out the PCI device, and map its memory and I/O address.
* It will understand both DEC21x4x and FEI type cards.
*
* RETURNS: N/A
*/

STATUS sysLanPciInit (void)
{
    PciDevice *         pDev;           /* Pci resources */
    PCI_RESOURCES *	pRsrc;		/* dec resource */
    UINT32		pciBus;		/* PCI Bus number */
    UINT32		pciDevice = 0;	/* PCI Device number */
    UINT32		pciFunc;	/* PCI Function number */
    unsigned int	ix;		/* counter */
    int			iy;		/* counter */
    int			unit = 0;	/* unit numbers */
    UINT32		boardType = NONE; /* board type detected */
#ifdef INCLUDE_FEI82557END
    FEI_RESOURCE *      pFeiRes;        /* FEI specific info */
#endif

    /* Setup Interrupt Pointers */
    feiEndIntConnect = (FUNCPTR) pciIntConnect;
    feiEndIntDisconnect = (FUNCPTR) pciIntDisconnect;

    /*
     * The following code tries to automatically detect and configure
     * all instances of supported Ethernet cards.
     */

    for (ix = 0; ix < BOARD_TYPE_NB; ix++)
        {
        for (iy = 0; iy < PCI_MAX_DEV; iy++)
            {
            if( (pDev = pciDeviceGet(boardResources[ix].vendorId,
                   boardResources[ix].deviceId, iy) ) == NULL)
                break;	/* skip to next vendor/product pair */

            if( pDev->error == TRUE )
                {
                break;  /* Something wrong here */
                }

            /* board detected */
            boardType = boardResources[ix].type;
            pciBus = pDev->bus;
            pciDevice = pDev->device;
            pciFunc = pDev->func;

            /*
             * Update the END device table
             *
             * pciDevice for PCI cards plugged in is in the range 5 to 8.
             */
            pRsrc = &(pciResources[pciDevice]);

            /* We only do Auto Configuration */
            /* get memory base address and I/O base address */

#ifdef INCLUDE_DEC21X40END
            if ((boardType >= DEC_START) &&
                (boardType < (DEC_START + TYPE_ALLOC)))
                {

                pRsrc->iobaseCsr = pDev->bar[0].address;
 
                pRsrc->membaseCsr = pDev->bar[1].address;

                pRsrc->irq = pDev->irq;

                pRsrc->iobaseCsr &= ~CSR_BASE_MSK;
                pRsrc->membaseCsr &= ~CSR_BASE_MSK;

                /* overwrite the resource table with read value */

                pRsrc->irqvec       = IVEC_TO_INUM(pRsrc->irq);
                }

#endif /* INCLUDE_DEC21X40END */

#ifdef INCLUDE_FEI82557END

            if ((boardType >= FEI_START) &&
                 (boardType < (FEI_START + TYPE_ALLOC)))
                {
                pFeiRes = &feiResources [unit];

                pFeiRes->pciBus    = pciBus;
                pFeiRes->pciDevice = pciDevice;
                pFeiRes->pciFunc   = pciFunc;

                pFeiRes->membaseCsr = pDev->bar[0].address;

                if (sysMmuMapAdd(sysPciToPhys((void *)pFeiRes->membaseCsr), pDev->bar[0].size,
                        FEI_INIT_STATE_MASK, FEI_INIT_STATE) == ERROR)
                    {
                    /* This error condition will be checked in the attach */
                    pDev->error = TRUE;
                    break;
                    }

                /* Convert to CPU address */
                pFeiRes->membaseCsr += CPU_PCI_MEM_ADRS;
#define PCI_IO_ADRS_OK
#ifdef PCI_IO_ADRS_OK
                pFeiRes->iobaseCsr = pDev->bar[1].address;
                pFeiRes->iobaseCsr &= ~PCI_BASE_IO;
                pFeiRes->iobaseCsr += CPU_PCI_IO_ADRS;
#else
                pFeiRes->iobaseCsr = pFeiRes->membaseCsr;
#endif

                pFeiRes->membaseFlash = pDev->bar[2].address;
                if (sysMmuMapAdd(sysPciToPhys((void *)pFeiRes->membaseFlash), pDev->bar[2].size,
                        FEI_INIT_STATE_MASK, FEI_INIT_STATE) == ERROR)
                    {
                    /* This error condition will be checked in the attach */
                    pDev->error = TRUE;
                    break;
                    }
                pFeiRes->membaseFlash += CPU_PCI_MEM_ADRS;

                pFeiRes->irq = pDev->irq;
 
                pFeiRes->configType = boardType;

                }
#endif /* INCLUDE_FEI82557END */

            /*
             * Update the END device table & dynamically create the load
             * string we need for this device
             */

#ifdef INCLUDE_DEC21X40END
            if ((boardType >= DEC_START) &&
                (boardType < (DEC_START + TYPE_ALLOC)))
                {
                /*
                 * END load string format:
                 *  "<deviceAddr>:<pciAddr>:<iVec>:<iLevel>:<numRds>:<numTds>:\
                 *  <memBase>:<memSize>:<userFlags>:<phyAddr>:<pPhyTbl>:\
                 *  <phyFlags>:<offset>"
                 */
                pRsrc->cpuToPciOffset = PCI2DRAM_BASE_ADRS - SDRAM_PHYS_BASE;

                pRsrc->buf = (void *)NONE;

                sprintf (endLoadStr[currentEndDevice],
                         "%#x:%#x:%#x:%#x:-1:-1:%#x:%#x:%#x:%#x:%#x:%#x:2:-1:0:",
                         /* Note: unit is prepended by the mux driver */
                         pRsrc->iobaseCsr + CPU_PCI_IO_ADRS,
                         pRsrc->cpuToPciOffset,
                         pRsrc->irq, pRsrc->irqvec,
                         (UINT32)pRsrc->buf, 0,
                         boardResources[ix].decUsrFlags,
                         1, 0,                       /* phyAddr,pMiiPhyTbl,*/
                         DEC_USR_MII_10MB  |
                         DEC_USR_MII_HD    | DEC_USR_MII_100MB |
                         DEC_USR_MII_FD    | DEC_USR_MII_BUS_MON
                        );

                endDevTbl[currentEndDevice].unit = unit++;
                endDevTbl[currentEndDevice].endLoadFunc = dec21x40EndLoad;
                endDevTbl[currentEndDevice].endLoadString =
                            endLoadStr[currentEndDevice];
                endDevTbl[currentEndDevice].endLoan = DEC_BUFF_LOAN;

                currentEndDevice++;

                /* enable mapped memory and I/O addresses */

                pciConfigOutWord (pciBus, pciDevice, pciFunc, PCI_CFG_COMMAND,
                      PCI_CMD_IO_ENABLE | PCI_CMD_MASTER_ENABLE);

                /* disable sleep mode */

                pciConfigOutByte (pciBus, pciDevice, pciFunc, PCI_CFG_MODE,
                      SLEEP_MODE_DIS);
                }
#endif /* INCLUDE_DEC21X40END */

#ifdef INCLUDE_FEI82557END
            if ((boardType >= FEI_START) &&
                (boardType < (FEI_START + TYPE_ALLOC)))
                {
                pRsrc->buf = (void *)NONE;

                sprintf (endLoadStr[currentEndDevice],
                        "0x%08X:0x0:0x0:0x0:0x00:2",
                        (UINT32)pRsrc->buf);

                endDevTbl[currentEndDevice].unit = unit++;
                endDevTbl[currentEndDevice].endLoadFunc = fei82557EndLoad;
                endDevTbl[currentEndDevice].endLoadString =
                                                endLoadStr[currentEndDevice];
                endDevTbl[currentEndDevice].endLoan = 1;
                currentEndDevice++;

                /* enable mapped I/O addresses */

                pciConfigOutWord (pciBus, pciDevice, pciFunc,
                          PCI_CFG_COMMAND, PCI_CMD_IO_ENABLE | PCI_CMD_MEM_ENABLE |
                          PCI_CMD_MASTER_ENABLE);

                feiUnits++;
                }
#endif /* INCLUDE_FEI82557END */

            /* Configured the maximum number of adaptors? */

            if (currentEndDevice == PCI_MAX_DEV)
                {
                return OK;
                }
            }
        }

    if ((unit == 0) || (pciDevice > PCI_MAX_DEV))
        {
        return ERROR;
        }

    return OK;
    }

#ifdef INCLUDE_DEC21X40END

/*******************************************************************************
*
* sysLanIntEnable - enable dec21X4X interrupts
*
* This routine enables dec21X4X interrupts.  This may involve operations on
* interrupt control hardware.
*
* RETURNS: OK or ERROR for invalid arguments.
*/

STATUS sysLanIntEnable
    (
    int	level		/* level number */
    )
    {
    return (intEnable(level));
    }

/*******************************************************************************
*
* sysLanIntDisable - disable dec21X4X interrupts
*
* This routine disables dec21X4X interrupts.  This may involve operations on
* interrupt control hardware.
*
* RETURNS: OK or ERROR for invalid arguments.
*/

STATUS sysLanIntDisable
    (
    int	level		/* level number */
    )
    {
    return (intDisable(level));
    }

/*******************************************************************************
*
* sysDec21x40EnetAddrGet - get Ethernet address
*
* This routine provides a target-specific interface for accessing a
* device Ethernet address.
*
* RETURNS: OK or ERROR if could not be obtained.
*/

STATUS sysDec21x40EnetAddrGet
    (
    int		unit,
    char *	enetAdrs
    )
    {
    /*
     * There isn't a target-specific interface for accessing a
     * device Ethernet address.
     */

    return (ERROR);
    }

#endif /* INCLUDE_DEC21X40END */

#ifdef INCLUDE_FEI82557END

/*******************************************************************************
*
* sys557Init - prepare LAN adapter for 82557 initialization
*
* This routine is expected to perform any adapter-specific or target-specific
* initialization that must be done prior to initializing the 82557.
*
* The 82557 driver calls this routine from the driver attach routine before
* any other routines in this library.
*
* This routine returns the interrupt level the <pIntLvl> parameter.
*
* RETURNS: OK or ERROR if the adapter could not be prepared for initialization.
*/

STATUS sys557Init
    (
    int	unit,			/* unit number */
    FEI_BOARD_INFO * pBoard     /* board information for the end driver */
    )
{
    volatile FEI_RESOURCE * pReso = &feiResources [unit];
    UINT16	sum          = 0;
    int		ix;
    int		iy;
    UINT16	value;
    void *	testbuf = 0;	/* keep compiler quite */

    /*
     * Locate the 82557 based adapter - PRO100B, INBUSINESS and XXX.
     * Note that since the INBUSINESS adapter is based upon the PRO100B
     * board type, it is initialised and driven like one.
     */

    if (pReso->boardType != UNKNOWN)		/* only setup once */
	{
	}
    else
	{
	/* read the configuration in EEPROM */

/*
 * According to intel, the checksum word is the last word in a 64 (0x40) word EEPROM.
 * It calculates the checksum accordoing to the formula: Checksum = 0XBABBA - (sum of the first 63 words).
 *
 * Currently it does not appear as though the checksum being burned into the EEPROM is valid...
 */
        for (ix = 0; ix < EE_SIZE; ix++)
            {
            value = sys557eepromRead (unit, ix);
            pReso->eeprom[ix] = value;
            sum += value;
            }

        if(pReso->configType == PRO100B)
            {
            if (sum != EE_CHECKSUM)
              printf ("i82557(%d): Invalid EEPROM checksum, sum: %#4.4x, checksum: %#4.4x, read: %#4.4x\n", 
                      unit, sum, (UINT16)(EE_CHECKSUM - sum), pReso->eeprom[0x3f]);

            /* DP83840 specific setup */
            if (((pReso->eeprom[6]>>8) & 0x3f) == DP83840)
                {
                int reg23 = sys557mdioRead (unit, pReso->eeprom[6] & 0x1f, 23);
                sys557mdioWrite (unit, pReso->eeprom[6] & 0x1f, 23, reg23 | 0x0420);
                }
            }

	/* perform a system self-test. */

        pReso->timeout = 16000;		/* Timeout for self-test. */

	/*
	 * No specific area specified, so we assume that cacheDmaMalloc() will
	 * return a pointer to a suitable area. If the data cache is on,
	 * this will be page-aligned, but if the data cache is off, then we
	 * will just get whatever malloc returns.
	 */

	if (testbuf = cacheDmaMalloc (32), testbuf == 0)
	    {
	    printf("fei%d cacheDmaMalloc failed\n", unit);
	    return ERROR;
	    }
	pReso->pResults = (volatile INT32 *)testbuf;


	/* The chip requires the results buffer to be 16-byte aligned. */

        pReso->pResults    = (volatile INT32 *)
			     ((((int) pReso->pResults) + 0xf) & ~0xf);

	/* initialise results buffer */

	pReso->pResults[0] = 0;
	pReso->pResults[1] = -1;

	/* Issue the self-test command */
	sysOutLong (pReso->iobaseCsr + SCB_PORT, (int)pReso->pResults | 1);

	/* wait for results */
	do
	    {
	    sysDelay();		/* cause a delay of at least an I/O cycle */
	    }
	while ((pReso->pResults[1] == -1) && (--pReso->timeout >= 0));

        pReso->boardType = PRO100B;	/* note that it is now initialised */

        /* Save results so we can refer to them again later */

        pReso->str[0] = pReso->pResults[0];
        pReso->str[1] = pReso->pResults[1];

        cacheDmaFree (testbuf);

        pReso->pResults = pReso->str;

	}