syslib.c

vxworks的BSP开发配置文件

* This routine returns the model name of the CPU board.
*
* RETURNS: A pointer to a string identifying the board and CPU.
*/

char * sysModel (void)
    {
    return "Intel IXM1200 - ARM IXM1200";
    }

/*******************************************************************************
*
* sysBspRev - return the BSP version with the revision eg 1.1/<x>
*
* This function returns a pointer to a BSP version with the revision.
* for eg. 1.1/<x>. BSP_REV is concatenated to BSP_VERSION to form the
* BSP identification string.
*
* RETURNS: A pointer to the BSP version/revision string.
*/

char * sysBspRev (void)
    {
    return (BSP_VERSION BSP_REV);
    }

/*******************************************************************************
*
* ixmVersion - return the Intel IXM version
*
* This function returns a pointer to a BSP version with the revision.
* This is the Intel IXM version in the form "major.minor.build_num".
*
* RETURNS: A pointer to the BSP version/revision string.
*/

char * ixmVersion (void)
    {
    return (IXM_VERSION);
    }

/*******************************************************************************
*
* sysCpuIDGet - return the CPU ID
*
* This function returns the CPU ID. The low order 4-bits gives the revision
* number.
*
* RETURNS: CPU ID
*/

int sysCpuIDGet (void)
    {
    return (sysCpuId);
    }

/*******************************************************************************
*
* sysBoardIDGet - return the Board ID
*
* This function returns the Board ID.
*
* RETURNS: Board ID
*/

int sysBoardIDGet (void)
    {
    return (0x80860000 | SI_SYS_ID);
    }

/*******************************************************************************
*
* sysTorCommMethod - return method tornado is using for communications
*
* This function returns the method that tornado will use for communications.
*
* RETURNS: comm method:
*          0: Unknown
*          1: Serial Port
*          2: ethernet
*          3: HPC
*/

int sysTorCommMethod (void)
    {
#if (WDB_COMM_TYPE == WDB_COMM_SERIAL)
# if (WDB_TTY_CHANNEL == 0)
    return 1;
# else
    return 3;
# endif
#elif (WDB_COMM_TYPE == WDB_COMM_NETWORK)
    return 2;
#else
    return 0;
#endif
    }

/******************************************************************************
*
* sysVirtToPhys - translate a virtual address to a physical address (ARM)
*
* This function converts a virtual address (of part of a page table in
* DRAM) to a physical address. This routine is used both by the BSP MMU
* initialisation and by the vm(Base)Lib code later (via function
* pointer). The mapping set up in the initial BSP MMU initialisation is
* the same as that done later and that done previously by Angel.
*
* RETURNS: the physical adddress
*/

void * sysVirtToPhys
    (
    void *	virtAddr	/* virtual address in DRAM */
    )
    {
    if (((UINT32) virtAddr) < ROM_VIRT_OFFSET)
        {

        /* SDRAM */

        return (void *) (((UINT32) virtAddr) + SDRAM_VIRT_OFFSET);
        }
    else if (((UINT32) virtAddr) < SRAM_BASE)
        {

        /* Flash */

        return (void *) (((UINT32) virtAddr) - ROM_VIRT_OFFSET);
        }
    else
        {
        return virtAddr;
        }
    }

/******************************************************************************
*
* sysPhysToVirt - translate a physical address to a virtual address (ARM)
*
* This function converts a physical address (of part of a page table in
* DRAM) to a virtual address. This routine is used by the vm(Base)Lib
* code later (via function pointer).
*
* RETURNS: the virtual adddress
*/

void * sysPhysToVirt
    (
    void *	physAddr	/* physical address in DRAM */
    )
    {
    if (((UINT32) physAddr) < SRAM_BASE)
        {

        /* Flash */

        return (void *) (((UINT32) physAddr) + ROM_VIRT_OFFSET);
        }
    else if ((((UINT32) physAddr) >= SDRAM_VIRT_OFFSET) &&
             (((UINT32) physAddr) <  SDRAM_PF_BASE))
        {

        /* SDRAM */

        return (void *) (((UINT32) physAddr) - SDRAM_VIRT_OFFSET);
        }
    else
        {
        return physAddr;
        }
    }


/******************************************************************************
*
* sysHwInit0 - Intialize _func_armVirtToPhys before sysHwInit is called
*
* This function initialized _func_armVirtToPhys and _func_armPhysToVirt
* before sysHwInit is called. It is called from usrInit in bootConfig.c
* before cacheLibInit is called.
*
* RETURNS: N/A
*/

void sysHwInit0()
    {
#ifndef TOR201
    _func_armVirtToPhys = sysVirtToPhys;
    _func_armPhysToVirt = sysPhysToVirt;
#else
#if defined(INCLUDE_CACHE_SUPPORT) || defined(INCLUDE_MMU)
    /*
     * Install the appropriate cache libary, using the our
     * address translation routines.
     */

    cacheArmSA1100LibInstall(sysPhysToVirt, sysVirtToPhys);
#endif
#ifdef INCLUDE_MMU
    /* Install the appropriate MMU library and translation routines */

    mmuArmSA1100LibInstall (sysPhysToVirt, sysVirtToPhys);
#endif /* INCLUDE_MMU */
#endif
    }

/*******************************************************************************
*
* sysHwInit - initialise the CPU board hardware
*
* This routine initialises various features of the hardware.
* Normally, it is called from usrInit() in usrConfig.c.
*
* NOTE: This routine should not be called directly by the user.
*
* RETURNS: N/A
*/

void sysHwInit (void)
    {
    UINT32 gpio_en;
#ifdef INCLUDE_EARLY_SERIAL_DEBUG
    UINT32 csr;
#endif

    /* install the IRQ/SVC interrupt stack splitting routine */

    _func_armIntStackSplit = sysIntStackSplit;

    DEBUG_LED(6);


    /* Initialize sysCpuRev */

    sysCpuId = sysCpuVerGet();
    sysCpuRev = sysCpuId & 0xF;


    /* Initialize flash32BitMode (equals ~ GPIO[3]) */
    IXM1200_REG_READ(IXM1200_GPIO_EN, gpio_en);
    IXM1200_REG_WRITE(IXM1200_GPIO_EN, GPIO_OWN_CCCC | GPIO_OUTPUT(0));
    IXM1200_REG_READ(IXM1200_GPIO_DATA, sysGPIOVal);
    IXM1200_REG_WRITE(IXM1200_GPIO_EN, gpio_en);
    if ((sysGPIOVal & (1<<3)) && (sysCpuRev > 0))
        flash32BitMode = 0;
    else
        flash32BitMode = 1;


    /* Deassert external reset, now that we've read GPIOs */
    IXM1200_REG_WRITE(RESET_MICROENGINE, IXM1200_RESET);

    /* Initialize sysPhysMemDescNumEnt */

    while (sysPhysMemDesc[sysPhysMemDescNumEnt-1].len == 0)
        sysPhysMemDescNumEnt--;


    /* initialize HPC */
#ifdef INCLUDE_HPC
    if (!(sysStartType & BOOT_DONT_INIT_HPC)) {
        hpcMemInit();
    }
#else
    hpcMemDummyInit();
#endif


    /* initialize PCI unit */
    if (!(sysStartType & BOOT_DONT_INIT_PCI))
        sysPciInit();

    DEBUG_LED(0xB);

#if defined (INCLUDE_SERIAL)
    /* initialise the appropriate serial devices */

    sysSerialHwInit ();      /* initialise serial data structure */
#else

    /* Quiet UART Interrupts */

    IXM1200_REG_WRITE(IXM1200_UART_CR, 0);
#endif

#ifdef INCLUDE_EARLY_SERIAL_DEBUG
    dbgSerInit();

	dbgSerOutstr("BSP IXM Version: ");
	dbgSerOutstr(ixmVersion());
	dbgSerOutstr(", built on ");
	dbgSerOutstr(creationDate);
	dbgSerOutstr("\r\n");
    {
        char buf[16];
        sprintf(buf,"%08X",sysCpuId);
        dbgSerOutstr("CPU ID: ");
        dbgSerOutstr(buf);
        dbgSerOutstr("\r\n");
        dbgSerOutstr("CPU Speed: ");
        /*
         * IXM1200 & Eval Board runs at:
         * <= C0 (rev 3): 200 MHz
         * >  C0 (rev 3): 232 MHz
         */
        if (sysCpuRev <= 3)
            dbgSerOutstr("200");
        else
            dbgSerOutstr("233");
        dbgSerOutstr(" MHz\r\n");
        if (sysCpuRev >= 5) {
            IXM1200_REG_READ(IXM1200_SDRAM_CSR, csr);
            if (csr & (1 << SDRAM_EN_ECC_BIT)) {
                dbgSerOutstr("ECC Enabled\r\n");
            }
        }
    }
    dbgSerOutstr("Early serial debug initialized\r\n");
#endif


#ifndef TOR201
#if defined(INCLUDE_MMU_BASIC) || defined(INCLUDE_MMU_FULL)

    /* initialise function pointers used by mmuLib */

    _func_armVirtToPhys = sysVirtToPhys;
    _func_armPhysToVirt = sysPhysToVirt;

    cacheLib.dmaPhysToVirtRtn	= (FUNCPTR) _func_armPhysToVirt;
    cacheLib.dmaVirtToPhysRtn	= (FUNCPTR) _func_armVirtToPhys;
#endif
#endif

#if defined (INCLUDE_PCI)

#if (_BYTE_ORDER == _BIG_ENDIAN)
    if (sysCpuRev < 1) {
#ifdef INCLUDE_EARLY_SERIAL_DEBUG
        dbgSerOutstr("Big Endian support requires CPU revision 1 or higher.\n\r");
#endif
        sysToMonitor(BOOT_NO_AUTOBOOT);
    }
#endif

    /* Initialize PCI driver library */

    if (pciIomapLibInit (PCI_MECHANISM_3,
                         PCI_CONFIG0_BASE,
                         PCI_CONFIG1_BASE,
                         0) != OK)
        sysToMonitor(BOOT_NO_AUTOBOOT);

    if (!(sysStartType & BOOT_DONT_INIT_PCI))
        sysIntel21555PreInit (DEF21555_US_WINDOW_SIZE);

#if defined (AUTO_PCI_CONFIG)
    if (!(sysStartType & BOOT_DONT_INIT_PCI))
            sysPciAssignAddrs();
        else
                readBarsAddrs();
#endif

    /* Read CSR IO Base for 21555 */
    readCsrIoBase ();

#if defined(INCLUDE_FEI82557END) || defined(INCLUDE_DEC21X40END)
    sysLanPciInit ();
#endif

    if (!(sysStartType & BOOT_DONT_INIT_PCI))
      sysIntel21555PostInit (SI_VEND_ID, SI_SYS_ID, DEF21555_DS_WINDOW_SIZE, DEF21555_DS_WINDOW_OFFSET);

#endif  /* INCLUDE_PCI */

    /* Quiet PCI Interrupts */

    IXM1200_REG_WRITE(IXM1200_IRQENABLECLEAR, 0xFFFFFFFF);
    IXM1200_REG_WRITE(IXM1200_FIQENABLECLEAR, 0xFFFFFFFF);

    /* Fix C0/Hyannis PCI CSR bug */
    *(volatile int*)(IXM1200_RESET);

    /* Quiet FBI Interrupts */

    IXM1200_REG_WRITE(IXM1200_IREG, 0);

    /* Quiet RTC Interrupts */

    IXM1200_REG_WRITE(IXM1200_RTC_DIV, RTCDIV_RESET_VAL);

    DEBUG_LED(7);

    return;
    }

/*******************************************************************************
*