syslib.c

vxworks的BSP开发配置文件

/* sysLib.c - Intel ixm1200 system-dependent routines */

/* Copyright 1997-1998 Wind River Systems, Inc.; Copyright 1999 Intel Corp. */
#include "copyright_wrs.h"

/*
modification history
--------------------
01h,10jul02,scm  bspVal mod: change sys_timer_clk so pkLib could be built
                 correctly...
01g,24jan02,scm  remove warnings...
01f,12sep01,scm  Allow variable bridge configurations...
01e,30aug01,scm  adjust naming conventions...
01d,07Mar00,jdg  Added support for B0 revision ixp1200
01c,05Jan00,jdg  Added support for auto PCI address assignment
01b,13aug99,jdg  changed name from vbsa1200 to ixp1200eb
01a,19apr99,jdg  created from 01e of brutus.
*/

/*
DESCRIPTION
This library provides board-specific routines for the Intel ixm1200 board.

It #includes the following chip drivers:
    ixm1200Timer.c - timer drivers
    ixm1200IntrCtl.c -	interrupt controller driver
    ixm1200Sio.c -       Serial I/O driver
    ixm1200Pci.c -       PCI unit driver
if INCLUDE_FLASH is defined, it #includes
    nvRamToFlash.c -	driver to use some Flash like NVRAM
else it #includes
    nullNvRam.c -	dummy NVRAM routines

It #includes the following BSP files:
    sysSerial.c -	serial device initialisation routines
    sysEnd.c -          END network driver support routines


INCLUDE FILES: sysLib.h string.h intLib.h vxLib.h cacheLib.h
muxLib.h config.h private/vmLibP.h arch/arm/mmuArmLib.h dllLib.h
pciIomapLib.h

SEE ALSO:
*/

/* includes */

#include "vxWorks.h"
#include "config.h"

#include "sysLib.h"
#include "intLib.h"
#include "string.h"
#include "vxLib.h"
#include "cacheLib.h"
#include "private/vmLibP.h"
#include "arch/arm/mmuArmLib.h"
#include "muxLib.h"
#include "dllLib.h"
#include "pciIomapLib.h"
#include "drv/mem/flash29.h"
#include "hpcIf.h"
#ifdef INCLUDE_EARLY_SERIAL_DEBUG
#include <stdio.h>
#endif

/* defines */

#ifdef USE_LEDS_FOR_DEBUG
#define DEBUG_LED(val) IXM1200_REG_WRITE(IXM1200_LED_ADDR, (val))
#else
#define DEBUG_LED(val)
#endif

#define MEM_DESC(vaddr,paddr,size,attr) \
    {(void *) (vaddr), (void *) (paddr), ROUND_UP((size), PAGE_SIZE), \
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE, \
         (attr)}
#define ATTR_WC (VM_STATE_VALID | VM_STATE_WRITABLE     | VM_STATE_CACHEABLE    )
#define ATTR_RC (VM_STATE_VALID | VM_STATE_WRITABLE_NOT | VM_STATE_CACHEABLE    )
#define ATTR_RM (VM_STATE_VALID | VM_STATE_WRITABLE_NOT | VM_STATE_CACHEABLE_MINICACHE)
#define ATTR_WN (VM_STATE_VALID | VM_STATE_WRITABLE     | VM_STATE_CACHEABLE_NOT)
#define ATTR_RN (VM_STATE_VALID | VM_STATE_WRITABLE_NOT | VM_STATE_CACHEABLE_NOT)
#define ATTR_INV (VM_STATE_VALID_NOT | VM_STATE_WRITABLE_NOT | VM_STATE_CACHEABLE_NOT)

/* imports */

IMPORT char end;		  	   /* end of system, created by ld */
IMPORT VOIDFUNCPTR _func_armIntStackSplit; /* ptr to fn to split stack */
IMPORT UINT32 sysMmuTtbrGet (void);	   /* read MMU TTBR register */
IMPORT void sysToRomInit(int bootType);    /* Branch to romInit after turning off
                                              the MMU */
IMPORT UINT16	sysRead16  (volatile UINT16 * ptr);
IMPORT void	    sysWrite16 (volatile UINT16 * ptr, UINT16 val);
IMPORT UINT32   swap32(UINT32 data);
IMPORT UINT16   swap16(UINT16 data);
IMPORT void     sysIntStackSplit (char *, long);
IMPORT void     pciCsrWr(void*, UINT32);
IMPORT char*    creationDate;
IMPORT int      sysStartType;

IMPORT int      sysCpuVerGet(void);    /* Read CPU HW revision */

/* globals */

#if !defined(INCLUDE_MMU) && \
    (defined(INCLUDE_CACHE_SUPPORT) || defined(INCLUDE_MMU_BASIC) || \
     defined(INCLUDE_MMU_FULL))
#define INCLUDE_MMU		/* should always be defined */
#endif

/*
 * The following variable describes which hardware CPU version we are
 * running on. Currently, the values are:
 *  0: A rev
 *  1: B rev
 *  3: C rev
 */

int sysCpuRev = 0;
int sysCpuId  = 0; /* Same as above but has all 32 bits */

/*
 * The following variable describes what flash mode we are in:
 * 0: 16-bit mode
 * 1: 32-bit mode
 *
 * In 16-bit mode, each flash read reads two 16-values and returns a 32-bit
 * result, whereas each flash write writes one 32-bit value. Note that the
 * flash offsets for reads are doubled by the hardware.
 */

int flash32BitMode = 0;

/*
 * The following variable holds the GPIO inputs, in case someone wants them
 * later
 */
int sysGPIOVal = 0;

/*
 * The following structure describes the various different parts of the
 * memory map, to be used during initialisation by vm(Base)GlobalMapInit()
 * when INCLUDE_MMU_BASIC or INCLUDE_MMU_FULL are defined.
 *
 * The following are not the smallest areas that could be allocated for a
 * working system. If the amount of memory used by the page tables is
 * critical, they could be reduced.
 */

PHYS_MEM_DESC sysPhysMemDesc [] =
    {
    /*
     * Address and length parameters must be page-aligned (multiples of 0x1000)
     * or else VxWorks will fail to boot, possibly silently.
     *
     * SDRAM: setup contiguously from 0 upwards.
     *   Start after RESERVED_LOW_MEM bytes, since the area below this is special
     */
    MEM_DESC(LOCAL_MEM_LOCAL_ADRS, SDRAM_VIRT_OFFSET, LOCAL_MEM_SIZE, ATTR_WC),
    /*
     * ROM / Flash: remapped to make room for SDRAM
     *
     * ROM is normally marked as uncacheable by VxWorks. We leave it
     * like that for the time being, even though this has a severe impact
     * on execution speed from ROM.
     *
     * In order to use the Flash as NVRAM, the Flash area must be
     * writable.  Strictly speaking, only the first and last pages need
     * be marked as writable.
     */

#ifdef INCLUDE_FLASH_UTILS

    /*
     * Map early pages, but make them invalid, this is needed to allow
     * for rewriting the entire flash later on.
     */

    MEM_DESC(FLASH_BASE,
             (FLASH_BASE - ROM_VIRT_OFFSET),
             ROM_BASE_ADRS-FLASH_BASE,
             ATTR_INV),
#endif

     MEM_DESC(ROM_BASE_ADRS, (ROM_BASE_ADRS-ROM_VIRT_OFFSET), ROM_SIZE, ATTR_RN),
#ifdef INCLUDE_FLASH

    /* The NVRAM page needs to be writable */

    MEM_DESC(FLASH_ADRS, (FLASH_ADRS-ROM_VIRT_OFFSET), FLASH_SIZE, ATTR_WN),

    /* The following pages need to be writable so that the FLASH29 tests work */

    MEM_DESC(ROUND_DOWN(FLASH29_REG_FIRST_CYCLE, PAGE_SIZE),
             ROUND_DOWN(FLASH29_REG_FIRST_CYCLE, PAGE_SIZE)-ROM_VIRT_OFFSET,
             PAGE_SIZE,
             ATTR_WN),
    MEM_DESC(ROUND_DOWN(FLASH29_REG_SECOND_CYCLE, PAGE_SIZE),
             ROUND_DOWN(FLASH29_REG_SECOND_CYCLE, PAGE_SIZE)-ROM_VIRT_OFFSET,
             PAGE_SIZE,
             ATTR_WN),

#endif

#ifdef INCLUDE_ALT_FLASH

    /*
     * Map address of alternate flash (using CE1) so we can boot from
     * NetROM and rewrite the flash on the board.
     */

    MEM_DESC(ALT_FLASH_BASE, (ALT_FLASH_BASE-ROM_VIRT_OFFSET), ALT_FLASH_SIZE,
             ATTR_RN),
#endif

    /* The rest of memory is flat, but do not map all of it, otherwise
       we will use up too much memory for page tables */
    /* SRAM */
    /* Details: SRAM_POP area is only one page (one word) long.
                The Read-Lock, CAM-Unlock, and Pop areas are ReadOnly */
    MEM_DESC(SRAM_BASE,         SRAM_BASE,         SRAM_SIZE, ATTR_WN),
    MEM_DESC(SRAM_RL_BASE,      SRAM_RL_BASE,      SRAM_SIZE, ATTR_RN),
    MEM_DESC(SRAM_WU_BASE,      SRAM_WU_BASE,      SRAM_SIZE, ATTR_WN),
    MEM_DESC(SRAM_CU_BASE,      SRAM_CU_BASE,      SRAM_SIZE, ATTR_RN),
    MEM_DESC(SRAM_BWC_BASE,     SRAM_BWC_BASE,     SRAM_SIZE, ATTR_WN),
    MEM_DESC(SRAM_BWS_BASE,     SRAM_BWS_BASE,     SRAM_SIZE, ATTR_WN),
    MEM_DESC(SRAM_BTC_BASE,     SRAM_BTC_BASE,     SRAM_SIZE, ATTR_WN),
    MEM_DESC(SRAM_BTS_BASE,     SRAM_BTS_BASE,     SRAM_SIZE, ATTR_WN),
    MEM_DESC(SRAM_PUSH_BASE_Q0, SRAM_PUSH_BASE_Q0, SRAM_SIZE, ATTR_WN),
    MEM_DESC(SRAM_PUSH_BASE_Q1, SRAM_PUSH_BASE_Q1, SRAM_SIZE, ATTR_WN),
    MEM_DESC(SRAM_PUSH_BASE_Q2, SRAM_PUSH_BASE_Q2, SRAM_SIZE, ATTR_WN),
    MEM_DESC(SRAM_PUSH_BASE_Q3, SRAM_PUSH_BASE_Q3, SRAM_SIZE, ATTR_WN),
    MEM_DESC(SRAM_PUSH_BASE_Q4, SRAM_PUSH_BASE_Q4, SRAM_SIZE, ATTR_WN),
    MEM_DESC(SRAM_PUSH_BASE_Q5, SRAM_PUSH_BASE_Q5, SRAM_SIZE, ATTR_WN),
    MEM_DESC(SRAM_PUSH_BASE_Q6, SRAM_PUSH_BASE_Q6, SRAM_SIZE, ATTR_WN),
    MEM_DESC(SRAM_PUSH_BASE_Q7, SRAM_PUSH_BASE_Q7, SRAM_SIZE, ATTR_WN),
    MEM_DESC(SRAM_POP_BASE_Q0,  SRAM_POP_BASE_Q0,  PAGE_SIZE, ATTR_RN),
    MEM_DESC(SRAM_POP_BASE_Q1,  SRAM_POP_BASE_Q1,  PAGE_SIZE, ATTR_RN),
    MEM_DESC(SRAM_POP_BASE_Q2,  SRAM_POP_BASE_Q2,  PAGE_SIZE, ATTR_RN),
    MEM_DESC(SRAM_POP_BASE_Q3,  SRAM_POP_BASE_Q3,  PAGE_SIZE, ATTR_RN),
    MEM_DESC(SRAM_POP_BASE_Q4,  SRAM_POP_BASE_Q4,  PAGE_SIZE, ATTR_RN),
    MEM_DESC(SRAM_POP_BASE_Q5,  SRAM_POP_BASE_Q5,  PAGE_SIZE, ATTR_RN),
    MEM_DESC(SRAM_POP_BASE_Q6,  SRAM_POP_BASE_Q6,  PAGE_SIZE, ATTR_RN),
    MEM_DESC(SRAM_POP_BASE_Q7,  SRAM_POP_BASE_Q7,  PAGE_SIZE, ATTR_RN),

    MEM_DESC(SRAM_CSR_BASE,     SRAM_CSR_BASE,     PAGE_SIZE, ATTR_WN),
    MEM_DESC(SRAM_IO_BASE,      SRAM_IO_BASE,      IO_SIZE,   ATTR_WN),

#ifdef LED_MEM_MAPPED
    /* LED */
    MEM_DESC(ROUND_DOWN(IXM1200_LED_ADDR,PAGE_SIZE),
             ROUND_DOWN(IXM1200_LED_ADDR,PAGE_SIZE),
             PAGE_SIZE,
             ATTR_WN),
#endif

    /* System Registers */
    MEM_DESC(IXM1200_SYS_REG_BASE, IXM1200_SYS_REG_BASE, IXM1200_SYS_REG_SIZE, ATTR_WN),

    /* ATU registers */
    MEM_DESC(UENG_CSR_BASE,    UENG_CSR_BASE,    UENG_CSR_SIZE,    ATTR_WN),
    MEM_DESC(UENG_XFER_BASE,   UENG_XFER_BASE,   UENG_XFER_SIZE,   ATTR_WN),
    MEM_DESC(FBI_CSR_BASE,     FBI_CSR_BASE,     PAGE_SIZE,        ATTR_WN),
    MEM_DESC(FBI_SCRATCH_BASE, FBI_SCRATCH_BASE, FBI_SCRATCH_SIZE, ATTR_WN),

    /* SDRAM */
    /* SDRAM non-prefetch already done up above, except for low reserved mem */
    MEM_DESC(SDRAM_PHYS_BASE,  SDRAM_PHYS_BASE,  RESERVED_LOW_MEM, ATTR_WN),
    MEM_DESC(SDRAM_PF_BASE,    SDRAM_PF_BASE,    LOCAL_MEM_SIZE,   ATTR_WN),
    MEM_DESC(CACHE_FLUSH_BASE, CACHE_FLUSH_BASE, D_CACHE_SIZE,     ATTR_WC),
    MEM_DESC(MINICACHE_FLUSH_BASE, MINICACHE_FLUSH_BASE, PAGE_SIZE,ATTR_RM),
    MEM_DESC(SDRAM_CSR_BASE,   SDRAM_CSR_BASE,   PAGE_SIZE,        ATTR_WN),

    /* PCI Unit */
    MEM_DESC(PCI_CSR_BASE, PCI_CSR_BASE, PAGE_SIZE, ATTR_WN),

#ifdef INCLUDE_PCI
    MEM_DESC(CPU_PCI_CNFG_ADRS, CPU_PCI_CNFG_ADRS, CPU_PCI_CNFG_SIZE, ATTR_WN),
#if (PCI_MAX_BUS > 1)
    MEM_DESC(CPU_PCI_CNFG_1_ADRS, CPU_PCI_CNFG_1_ADRS, CPU_PCI_CNFG_1_SIZE, ATTR_WN),
#endif

#ifndef AUTO_PCI_CONFIG
    /* 1 page in PCI I/O Space for ethernet card CSRs */
    MEM_DESC(CPU_PCI_IO_ADRS, CPU_PCI_IO_ADRS, CPU_PCI_IO_SIZE, ATTR_WN),
#endif

#ifdef INCLUDE_EXTRA_PCI_MAPPING
	/* For PCI device driver -- drj: Oct 11,99 */
    MEM_DESC(CPU_PCI_MEM_ADRS, CPU_PCI_MEM_ADRS, CPU_PCI_MEM_SIZE, ATTR_WN),
#endif

#endif /* ifdef INCLUDE_PCI */

    /* Allocate space for sysMmuMapAdd */
    MEM_DESC(NULL, NULL, 0, 0),
    MEM_DESC(NULL, NULL, 0, 0),
    MEM_DESC(NULL, NULL, 0, 0),
    MEM_DESC(NULL, NULL, 0, 0),
    MEM_DESC(NULL, NULL, 0, 0),
    MEM_DESC(NULL, NULL, 0, 0),
    MEM_DESC(NULL, NULL, 0, 0),
    MEM_DESC(NULL, NULL, 0, 0),
    MEM_DESC(NULL, NULL, 0, 0),
    MEM_DESC(NULL, NULL, 0, 0),
    MEM_DESC(NULL, NULL, 0, 0),
    MEM_DESC(NULL, NULL, 0, 0),
    MEM_DESC(NULL, NULL, 0, 0),
    MEM_DESC(NULL, NULL, 0, 0),
    MEM_DESC(NULL, NULL, 0, 0),
    MEM_DESC(NULL, NULL, 0, 0),
    MEM_DESC(NULL, NULL, 0, 0),
    MEM_DESC(NULL, NULL, 0, 0),
    MEM_DESC(NULL, NULL, 0, 0),
    MEM_DESC(NULL, NULL, 0, 0),
    MEM_DESC(NULL, NULL, 0, 0),
    MEM_DESC(NULL, NULL, 0, 0),
    MEM_DESC(NULL, NULL, 0, 0),
    MEM_DESC(NULL, NULL, 0, 0),
    MEM_DESC(NULL, NULL, 0, 0),
    MEM_DESC(NULL, NULL, 0, 0),
    MEM_DESC(NULL, NULL, 0, 0),
    MEM_DESC(NULL, NULL, 0, 0),
    MEM_DESC(NULL, NULL, 0, 0),
    MEM_DESC(NULL, NULL, 0, 0),
    MEM_DESC(NULL, NULL, 0, 0),
    MEM_DESC(NULL, NULL, 0, 0),
    MEM_DESC(NULL, NULL, 0, 0),
    MEM_DESC(NULL, NULL, 0, 0),
    MEM_DESC(NULL, NULL, 0, 0),
    MEM_DESC(NULL, NULL, 0, 0),
    MEM_DESC(NULL, NULL, 0, 0),
    MEM_DESC(NULL, NULL, 0, 0),
    MEM_DESC(NULL, NULL, 0, 0),
    MEM_DESC(NULL, NULL, 0, 0),
    };

int sysPhysMemDescNumEntMax = NELEMENTS (sysPhysMemDesc);
int sysPhysMemDescNumEnt = NELEMENTS (sysPhysMemDesc);

int	sysBus	    = BUS;		/* system bus type (VME_BUS, etc) */
int	sysCpu	    = CPU;		/* system cpu type (ARMSA110) */
char *	sysBootLine = BOOT_LINE_ADRS; 	/* address of boot line */
char *	sysExcMsg   = EXC_MSG_ADRS;	/* catastrophic message area */
int	sysProcNum;			/* processor number of this cpu */
int	sysFlags;			/* boot flags */
char	sysBootHost [BOOT_FIELD_LEN];	/* name of host from which we booted */
char	sysBootFile [BOOT_FIELD_LEN];	/* name of file from which we booted */


/* locals */

/* forward declarations */

char * sysPhysMemTop (void);
int sysLedsReadWrite (int and, int eor);

STATUS sysMmuMapAdd(void *addr, UINT len, UINT mask, UINT state);
void * sysVirtToPhys(void *virtAddr);
void * sysPhysToVirt(void *physAddr);

/* included source files */

#ifdef INCLUDE_EARLY_SERIAL_DEBUG
#include "dbgSerUtils.c"
#endif

#include "sysSerial.c"
#include "ixm1200Timer.c"  /* was "timer/ambaTimer.c" */
#include "ixm1200IntrCtl.c"
#include "ixm1200Sio.c"
#include "ixm1200Pci.c"
#ifdef INCLUDE_FLASH
#include "mem/nvRamToFlash.c"
#else
#include "mem/nullNvRam.c"
#endif

#include "pciIomapLib.c"
#include "pciIomapShow.c"

#if defined(INCLUDE_FEI82557END) || defined(INCLUDE_DEC21X40END)
#include "sysEnd.c"

STATUS sysLanPciInit (void);
#endif

#include "21555drv.c"

#include "ixm1200HPC.c"
#ifdef INCLUDE_HPC_SERIAL
#include "HPCSerial.c"
#endif

/*******************************************************************************
*
* sysModel - return the model name of the CPU board
*