rominit.s

vxworks的BSP开发配置文件

	/* Set up the SDRAM
	 * Note that the SDRAM CSR must be the last one set
	 */

#if defined(PA1104)
	ADR	r1, L$_SDRAM_CONFIG_PARAMS_232
#else /* IXM1200 & Eval Boards */
	CMP	r8, #3
	ADRLE	r1, L$_SDRAM_CONFIG_PARAMS_200
	ADRGT	r1, L$_SDRAM_CONFIG_PARAMS_232
#endif
	LDMIA	r1, {r2-r6}	/* get parameters from table */
	STMIA	r2, {r4-r6}	/* store MEMCTL0, MEMCTL1, MEMINIT */
	CMP	r8, #6          /* See if we need to turn on ECC */
	ORREQ	r3, r3, #(1 << SDRAM_EN_ECC_BIT)
	STR	r3, [r2,#-(IXM1200_SDRAM_MEMCTL0 - IXM1200_SDRAM_CSR)]


#ifndef USE_LEDS_FOR_DEBUG

	/* Initialize LED's */

	LDR	r1, L$_IXM1200_LED_ADDR
#ifndef LED_MEM_MAPPED

	/*
	 * Set GPIO's to core ownership, outputs, and output a zero
	 * IXM1200_LED_ADDR is GPIO_DATA
	 */
	MOV	r2, #(GPIO_OWN_CCCC | GPIO_OUTPUT(0xF))
	STR	r2, [r1,#-(IXM1200_LED_ADDR-IXM1200_GPIO_EN)]
#endif /* LED_MEM_MAPPED */
	MOV	r2, #0
	STR	r2, [r1]
#endif /* USE_LEDS_FOR_DEBUG */


	/*
	 * If ECC is enabled, write to all of memory to initialize it
	 */
	CMP	r8, #6
	BNE	skipECC
	// avail regs:	 r1,2,3,sp
#ifdef USE_LEDS_FOR_DEBUG
	LDR	r1, L$_IXM1200_LED_ADDR
	MOV	r2, #3
	STR	r2, [r1]
#endif /* USE_LEDS_FOR_DEBUG */

	MOV	r1, #(LOCAL_MEM_SIZE_ACTUAL + SDRAM_PHYS_BASE)
	MOV	r2, #0
	MOV	r3, #0
	MOV	r4, #0
	MOV	r5, #0
	MOV	r6, #0
	MOV	r7, #0
	MOV	r8, #0
	MOV	r9, #0
ECCLoop:
	STMDB	r1!, {r2-r9}
	CMP	r1, #SDRAM_PHYS_BASE
	BNE	ECCLoop
skipECC:

#ifdef USE_LEDS_FOR_DEBUG
	LDR	r1, L$_IXM1200_LED_ADDR
	MOV	r2, #1
	STR	r2, [r1]
#endif /* USE_LEDS_FOR_DEBUG */


	/*
	 * Enable MMU and map sdram to 0. This is tricky because
	 * we also have to remap the addresses we are running out of.
	 * First copy the appropriate instructions from here to SDRAM,
	 * then when the MMU comes on line, there will be the same
	 * code in SDRAM
	 */

	/*
	 * Copy two instructions from ROM to SDRAM, starting at
	 * copy_start
	 */

	ADR	r1, copy_start
	LDMIA	r1, {r2-r3}

	/*
	 * The following two instructions implements:
	 * ADD	r1, r1, #SDRAM_VIRT_OFFSET
	 * but it must be broken into two instructions because otherwise
	 * the constant is too big
	 */

	ADD	r1, r1, #(SDRAM_VIRT_OFFSET & 0xff000000)
	ADD	r1, r1, #(SDRAM_VIRT_OFFSET & 0x00ff0000)

	STMIA	r1, {r2-r3}

	/* Get (physical) address of our Level 1 Page Table in the ROM. */

	LDR	r1, L$_romL1PTable
	MOV	r2, #0

	/*
	 * Read the Stack address and the boot rom address before we
	 * remap the MMU, so that we don't have to copy them into SDRAM
	 */

	LDR	r3, L$_rStrtInRom
	LDR	sp, L$_STACK_ADDR

	/*
	 * Write to the Translation Table Base Register in the MMU, to
	 * make these the current set of page tables and flush TLBs.
	*/

	MCR	CP_MMU, 0, r1, c2, c0, 0	/* Write the TTBR in MMU */
	MCR	CP_MMU, 0, r2, c8, c7, 0	/* Flush all I+D TLBs */

	MVN	r2, #0		                /* r0 <= 0xFFFFFFFF */
	MCR	CP_MMU, 0, r2, c3, c0, 0	/* Write the DACR in MMU */

	/* Enable the MMU */

	MRC	CP_MMU, 0, r1, c1, c0, 0	/* Read MMUCR */
	ORR	r1, r1, #MMUCR_M_ENABLE		/* Set MMU Enable bit */
	MCR	CP_MMU, 0, r1, c1, c0, 0	/* Write to MMU CR */

	/*
	 * We are now executing at the same virtual address, although
	 * the physical address is now in SDRAM.
	 * The caches are still switched off.
	 *
	 * Initialise the stack pointer to just before where the
	 * uncompress code, copied from ROM to RAM will run.
	 */

copy_start:
	MOV	fp, #0			/* zero frame pointer */

	/* jump to C entry point in ROM: routine - entry point + ROM base */

	MOV	pc, r3		/* L$_rStrtInRom, r0 = boot type */

/******************************************************************************/

	.balign	4

	/*
	 * PC-relative-addressable pointers - LDR Rn,=sym was (is?) broken
	 * note "_" after "$" to stop preprocessor performing substitution
	 */

L$_rStrtInRom:	.long	ROM_TEXT_ADRS + FUNC(romStart) - FUNC(romInit)

L$_STACK_ADDR:	.long	STACK_ADRS

L$_IXM1200_PPL_CFG:	.long IXM1200_PLL_CFG

#if !defined(PA1104)
L$_SRAM_CONFIG_PARAMS_200:
	.long IXM1200_SRAM_CSR	/* CSR address */
	.long SRAM_CSR
	.long SRAM_SLOW_CFG_200
	.long SRAM_FLASH_CFG_200
	.long SRAM_MAC_CFG

L$_SDRAM_CONFIG_PARAMS_200:
	.long IXM1200_SDRAM_MEMCTL0  /* SDRAM MEMCTL0 address */
	.long SDRAM_CSR
	.long SDRAM_MEMCTL0_200
	.long SDRAM_MEMCTL1_200
	.long SDRAM_MEMINIT_200
#endif

L$_SRAM_CONFIG_PARAMS_232:
	.long IXM1200_SRAM_CSR	/* CSR address */
	.long SRAM_CSR
	.long SRAM_SLOW_CFG_232
	.long SRAM_FLASH_CFG_232
	.long SRAM_MAC_CFG

L$_SDRAM_CONFIG_PARAMS_232:
	.long IXM1200_SDRAM_MEMCTL0  /* SDRAM MEMCTL0 address */
	.long SDRAM_CSR
	.long SDRAM_MEMCTL0_232
	.long SDRAM_MEMCTL1_232
	.long SDRAM_MEMINIT_232

L$_IXM1200_RESET:
	.long IXM1200_RESET

	/* IXM1200_LED_ADDR is either in memory or is the same as GPIO_DATA */

L$_IXM1200_LED_ADDR:
	.long IXM1200_LED_ADDR

L$_IXM1200_GPIO_EN:
	.long IXM1200_GPIO_EN

/* Make MMU Translation Table - Note: macro too deep when nested more than 64 */

#ifdef _DIAB_TOOL /* (TOOL_FAMILY == diab) */

MakeTransTable: .MACRO addr,addrSize,options,total
    .if total
       .if total <= 0x40
           .long ((addr << addrSize) | options)
           MakeTransTable (addr+1), addrSize, options, (total-1)
       .else
           .if total <= 0x256
               MakeTransTable addr, addrSize, options, 0x40
               MakeTransTable (addr+0x40), addrSize, options, (total-0x40)
           .else
               MakeTransTable addr, addrSize, options, 0x256
               MakeTransTable (addr+0x256), addrSize, options, (total-0x256)
           .endif
       .endif
    .endif
    .ENDM

#else  /* (TOOL_FAMILY == gnu) */

.MACRO MakeTransTable addr=0,addrSize=0,options=0,total=0
.if \total
   .if \total <= 0x40
       .long ((\addr << \addrSize) | \options)
       MakeTransTable "(\addr+1)", \addrSize, \options, "(\total-1)"
   .else
       .if \total <= 0x256
           MakeTransTable \addr, \addrSize, \options, 0x40
           MakeTransTable "(\addr+0x40)", \addrSize, \options, "(\total-0x40)"
       .else
           MakeTransTable \addr, \addrSize, \options, 0x256
           MakeTransTable "(\addr+0x256)", \addrSize, \options, "(\total-0x256)"
       .endif
   .endif
.endif
.ENDM

#endif /* _DIAB_TOOL */

/* Create First Level Section Descriptor */

#define SectionDesc(addr, options, total) \
        MakeTransTable addr, 20, options, total

/* Coarse page descriptor contains 14 bits, since it is easy to manipulate
 * the hex values, here the addr is shifted only by 12 bits, instead of 14bits.
 * So make sure that bit 11 and 10 are set to correctly in  options.
 * Bit 11 and 10 in options should contain the 2 LSBs from the coarse page address
 */

#define CoarsePageDesc(addr, options) \
        MakeTransTable addr, 12, options, 1

#define SmallPage(addr, options, total) \
        MakeTransTable addr, 12, options, total

	.balign	4

	/*
	 * The page table address needs to be a physical address, so
	 * remove the 08000000 offset that we are providing in the
	 * page table itself.
	 */

L$_romL1PTable:
	.long	(ROM_TEXT_ADRS + romL1PTable - FUNC(romInit)) & ~ROM_VIRT_OFFSET

	/*
	 * Page tables (actually section descriptors) to be used to
	 * remap machine so that RAM is contiguously arranged from 0
	 * upwards.
	 *
	 * Each entry corresponds to a megabyte of virtual address space
	 * and is a section descriptor, containing the physical address
	 * for the megabyte of virtual address space.
	 *
	 * A Level 1 page table must be 16 kilobyte-aligned WHEN IT IS IN
	 * THE FLASH DEVICE.
	 */

	.space	(0x4000 * \
		((. - FUNC(romInit) + (ROM_TEXT_ADRS - ROM_BASE_ADRS) + 0x3fff) \
		/ 0x4000)) - (ROM_TEXT_ADRS - ROM_BASE_ADRS) - (. - FUNC(romInit))

romL1PTable:

	/*
	 * First Map 128 Meg of SDRAM, starting after reserved area
	 * RAM_SECT_DESC is cacheable, OTHER_SECT_DESC is non-cacheable
	 * Map cache flush area (0xA0000000) as cacheable
	 */

/* Section Descriptions: address, options, total */
SectionDesc(0xC70, RAM_SECT_DESC, (0x080-0x000))

	/* Map 8 Meg of Flash */
SectionDesc(0x000, OTHER_SECT_DESC, (0x088-0x080))

	/* Map rest of memory flat */
SectionDesc(0x088, OTHER_SECT_DESC, (0xa00-0x088))

	/* Map cache flush area as cacheable */
SectionDesc(0xa00, RAM_SECT_DESC, (0xb00-0xa00))

	/* Map rest of memory flat */
SectionDesc(0xb00, OTHER_SECT_DESC, (0xe00-0xb00))

	/* Map E0000000 as invalid */
SectionDesc(0xe00, 0x0, (0xf00-0xe00))

	/* Map rest of memory flat */
SectionDesc(0xf00, OTHER_SECT_DESC, (0x1000-0xf00))