rominit.s

vxworks的BSP开发配置文件

/* romInit.s - Intel ixm1200 ROM initialisation module */

/* Copyright 1996-2002 Wind River Systems, Inc.; Copyright 1999 Intel Corp. */

/*
modification history
--------------------
01f,24jan02,scm  go over veloce mods...
01e,21jan02,j_b  Removed prepended underscores for new compilers (Diab/Gnu elf);
                 Replaced assembly .MACROs w/ C preprocessor #define macros
01d,30aug01,scm  adjust to reflect ixm1200...
01c,07Mar00,jdg  Added support for B0 revision ixp1200
01b,13aug99,jdg  Changed name from vbsa1200 to ixp1200eb
01a,08apr99,jdg  created from 01a of brutus
*/

/*
DESCRIPTION
This module contains the entry code for VxWorks images that start
running from ROM, such as 'bootrom' and 'vxWorks_rom'.
The entry point, romInit(), is the first code executed on power-up.
It performs the minimal setup needed to call the
generic C routine romStart() with parameter BOOT_COLD.

The routine romInit() masks interrupts in the processor, initialises
the MMU, sets the initial stack pointer (to STACK_ADRS which is defined
in configAll.h) and initialises system hardware including configuring
the DRAM controller. Other hardware and device initialisation is
performed later in the sysHwInit routine in sysLib.c.  The MMU
initialisation is more complex than for most BSPs, as we need to enable
the MMU, setting up some page tables, in order to map DRAM from zero
upwards, over the exception vectors.

The routine sysToMonitor() jumps to a location after the beginning of
romInit, (defined by ROM_WARM_ADRS) to perform a "warm boot". This
entry point allows a parameter to be passed to romStart().
It first has to disable the MMU, though, as romInit will disable it
during initialization.

The routines in this module don't use the "C" frame pointer %r11@ ! or
establish a stack frame.

SEE ALSO:
.I "ARM Architecture Reference Manual,"
*/

#define	_ASMLANGUAGE
#include "vxWorks.h"
#include "regs.h"
#include "arch/arm/arm.h"
#include "arch/arm/mmuArmLib.h"
#include "sysLib.h"
#include "config.h"

	.data
	.globl	VAR(copyright_wind_river)
	.long	VAR(copyright_wind_river)

	.data
	.align 4

	.globl  VAR(sdata)      /* start of data */
	.globl  _sdata

_sdata:
VAR_LABEL(sdata)
	.asciz  "start of data seg"

	.text
	.align  4

        /* globals */
	.globl	FUNC(romInit)	 /* start of system code */
	.globl  _romInit

	/* externals */
	.extern	FUNC(romStart)	/* system initialisation routine */

	.text
	.balign 4

/*******************************************************************************
*
* romInit - entry point for VxWorks in ROM
*
*
* romInit
*     (
*     int startType	/@ only used by 2nd entry point @/
*     )

* INTERNAL
* sysToMonitor examines the ROM for the first instruction and the string
* "Copy" in the third word so if this changes, sysToMonitor must be updated.
*/

_ARM_FUNCTION(romInit)
_romInit:
old:
	MOV	r0,#BOOT_COLD	/* fall through to warm boot entry */
warm:
	B	start

	/* copyright notice appears at beginning of ROM (in TEXT segment) */

	.ascii	"Copyright 1984-1998 Wind River Systems, Inc."
	.balign 4

start:
	/* disable interrupts in CPU and switch to SVC32 mode */

	MRS	r1, cpsr
	BIC	r1, r1, #MASK_MODE
	ORR	r1, r1, #MODE_SVC32 | I_BIT | F_BIT
	MSR	cpsr, r1

#if defined(PA1104) || defined(IXM1200)
	/*
	 * We need to make sure that reset out is asserted before we can
	 * read the GPIO's
	 */

	LDR	r1, L$_IXM1200_RESET
	LDR	r2, [r1]
	ORR	r2, r2, #RESET_EXTERNAL
	STR	r2, [r1]
#endif

	/* Read GPIO's into r7 */
	LDR	r1, L$_IXM1200_GPIO_EN
	MOV	r2, #(GPIO_OWN_CCCC | GPIO_OUTPUT(0))
	STR	r2, [r1]
	LDR	r7, [r1,#+(IXM1200_GPIO_DATA-IXM1200_GPIO_EN)]

#ifdef USE_LEDS_FOR_DEBUG

	/* Initialize LED's */

	LDR	r1, L$_IXM1200_LED_ADDR
#ifndef LED_MEM_MAPPED

	/*
	 * Set GPIO's to core ownership, outputs, and output a zero
	 * IXM1200_LED_ADDR is GPIO_DATA
	 */

	MOV	r2, #(GPIO_OWN_CCCC | GPIO_OUTPUT(0xF))
	STR	r2, [r1,#-(IXM1200_LED_ADDR-IXM1200_GPIO_EN)]
#endif /* LED_MEM_MAPPED */
	MOV	r2, #0
	STR	r2, [r1]
#endif /* USE_LEDS_FOR_DEBUG */


	/*
	 * Check for Chip revision: read chip ID into r8
	 * 0:	A rev
	 * 1:	B rev
	 * 3:	C rev
	 * 5:	D rev (Hyannis)
	 */

	MRC	CP_MMU, 0, r8, c0, c0, 0
	AND	r8,r8,#0xF


	/*
	 * if Hyannis and GPIO-2 is set, change the chip revision to 6
	 * to indicate that ECC should be enabled.
	 */

	CMP	r8, #5
	BNE	notHyannis
	TST	r7, #4
	ADDNE	r8, r8, #1
notHyannis:


	/*
	 * CPU INTERRUPTS DISABLED
	 *
	 * Set processor and MMU to known state as follows (we may have not
	 * been entered from a reset):
	 *
	 * MMU Control Register layout.
	 *
	 * bit
	 *  0 M 0 MMU disabled
	 *  1 A 0 Address alignment fault disabled, initially
	 *  2 C 0 Data cache disabled
	 *  3 W 0 Write Buffer disabled
	 *  4 P 1 Should Be One (PROG32 on earlier CPUs)
	 *  5 D 1 Should Be One (DATA32 on earlier CPUs)
	 *  6 L 1 Should Be One (Late abort on earlier CPUs)
	 *  7 B 0 Little-endian
	 *  8 S 0 System bit to zero } Modifies MMU protections, not really
	 *  9 R 1 ROM bit to one     } relevant until MMU switched on later.
	 * 10 F 0 Should Be Zero
	 * 11 Z 0 Should Be Zero (Branch prediction control on 810)
	 * 12 I 0 Instruction cache disabled
	 *
	 * Setup MMU Control Register
	 */

	MOV	r1, #MMU_INIT_VALUE
	MCR	CP_MMU, 0, r1, c1, c0, 0	/* Write to MMU CR */

	/*
	 * MMU is now off => addresses are physical addresses, no protection.
	 *
	 * If MMU was on before this, then we'd better hope it was set up
	 * for flat translation (at least of this code) or there will
	 * be problems. The next three instructions will still be
	 * fetched "translated".
	 *
	 * Set Process ID Register to zero, this effectively disables
	 * the process ID remapping feature.
	 */

	MOV	r1, #0
	MCR	CP_MMU, 0, r1, c13, c0, 0


	/*
	 * Set core clock speed in Power Manager PLL Configuration Register.
	 * This must be done before enabling clock switching - there are
	 * strong suspicions that it will have no effect otherwise.
	 */

	LDR	r1, L$_IXM1200_PPL_CFG	/* PLL Configuration Reg*/
#if defined(PA1104)
	MOV	r2, #CCF_232_24
#else /* IXM1200 & Eval Boards */
	CMP     r8, #3
	MOVLE	r2, #CCF_199_07
	MOVGT	r2, #CCF_232_24
#endif
	STR	r2, [r1]

	/*
	 * Put the CPU in its normal (fast) clock switching mode
	 * Note that this may prevent any kernel that a bootrom loads from
	 * changing the core clock.
	 */

	MCR	CP_MMU, 0, r14, c15, c1, 2

	/* Clear Debug Support features: VxWorks makes no use of these */

	MOV	r1, #0
	MCR	CP_MMU, 0, r1, c14, c3, 0	/* Clear DBCR */
	MCR	CP_MMU, 0, r1, c14, c8, 0	/* Clear IBCR */

	/*
	 * We would like to discard the contents of the Write-Buffer
	 * altogether, but there is no facility to do this. Failing that,
	 * we do not want any pending writes to happen at a later stage,
	 * so drain the Write-Buffer, i.e. force any pending writes to
	 * happen now.
	 */

	MCR	CP_MMU, 0, r1, c7, c10, 4	/* Drain write-buffer */

	/* Flush, (i.e. invalidate) all entries in all caches */

	MCR	CP_MMU, 0, r1, c7, c6, 0	/* Flush D-cache & mini-cache */
	MCR	CP_MMU, 0, r1, c7, c5, 0	/* Flush (inval.) all I-cache */

	/*
	 * On StrongARM, the next four instructions could still come
	 * from (what was in) the Instruction cache.
	 *
	 * The BSP makes no explicit use of Read Buffer, but make sure
	 * that nothing already in it affects us.
	 */

	MCR	CP_MMU, 0, r1, c9, c0, 0	/* Flush Read Buffer */


	/*
	 * Delay for a while to let the SDRAM clock PLL stabalize after
	 * the clock was changed above.
	 */

	MOV	r1, #0x40000
loop1:	SUBS	r1, r1, #1
	BNE	loop1


	/*
	 * Program SRAM Controller
	 * Note that we need to change SRAM_FLASH_CONFIG *before*
	 * SRAM_SLOW_CONFIG, otherwise, the timing parameters become
	 * inconsistent
	 */

#if defined(PA1104)
	ADR	r1, L$_SRAM_CONFIG_PARAMS_232
#else /* IXM1200 & Eval Boards */
	CMP	r8, #3
	ADRLE	r1, L$_SRAM_CONFIG_PARAMS_200
	ADRGT	r1, L$_SRAM_CONFIG_PARAMS_232
#endif
	LDMIA	r1, {r2-r6}	/* get parameters from table */
	STR	r3, [r2]	/* Write SRAM CSR */
	STR	r5, [r2,#+(IXM1200_SRAM_FLASH_CONFIG - IXM1200_SRAM_CSR)]
	STR	r6, [r2,#+(IXM1200_SRAM_MAC_CONFIG - IXM1200_SRAM_CSR)]
	STR	r4, [r2,#+(IXM1200_SRAM_SLOW_CONFIG - IXM1200_SRAM_CSR)]


	/* Bring other functional units out of reset */

	LDR	r1, L$_IXM1200_RESET
	MOV	r2, #RESET_MICROENGINE
#if defined(PA1104) || defined(IXM1200)
	/* Keep external reset applied so that sysHwInit can read GPIOs */
	ORR	r2, r2, #RESET_EXTERNAL
#endif
	STR	r2, [r1]