sysalib.s

vxworks的BSP开发配置文件

	LDR	r3, L$_vxSvcIntStackEnd
	STR	r2, [r3]			/*  == end of SVC-mode stack */
	SUB	r2, r0, r1, ASR #3		/* leave 1/8 for IRQ */
	LDR	r3, L$_vxSvcIntStackBase
	STR	r2, [r3]

	/* now allocate IRQ stack, setting irq_sp */

	LDR	r3, L$_vxIrqIntStackEnd
	STR	r2, [r3]
	LDR	r3, L$_vxIrqIntStackBase
	STR	r0, [r3]

	MRS	r2, cpsr
	BIC	r3, r2, #MASK_MODE
	ORR	r3, r3, #MODE_IRQ32 | I_BIT	/* set irq_sp */
	MSR	cpsr, r3
	MOV	sp, r0

	/* switch back to original mode and return */

	MSR	cpsr, r2
	MOV	pc, lr

/******************************************************************************
*
* sysMmuTtbrGet - get the Translation Table Base Register
*
* This routine reads the Translation Table Base Register of the MMU.
*
* RETURNS: the value in the TTBR
*
* NOMANUAL
*
*  LEVEL_1_DESC *  sysMmuTtbrGet(void)
*/

_ARM_FUNCTION_CALLED_FROM_C(sysMmuTtbrGet)

	MRC	CP_MMU, 0, r0, c2, c0, 0	/* Read the TTBR in MMU */
	MOV	pc, lr				/* exit */


/******************************************************************************
*
* sysCpuVerGet - get the CPU version
*
* This routine reads chip revision field from the coprocessor
*
* RETURNS: the CPU version
*
*/

_ARM_FUNCTION_CALLED_FROM_C(sysCpuVerGet)

	MRC	CP_MMU, 0, r0, c0, c0, 0
	MOV	pc, lr				/* exit */


/******************************************************************************
*
* sysToRomInit - turn off MMU and branch to romInit
*
* This copies a small bit of code to SDRAM
*
* RETURNS: This never returns
*
*
* void sysToRomInit
*     (
*     int startType
*     )
*/
_ARM_FUNCTION_CALLED_FROM_C(sysToRomInit)
	/* disable interrupts in CPU and switch to SVC32 mode */

	MRS	r1, cpsr
	BIC	r1, r1, #MASK_MODE
	ORR	r1, r1, #MODE_SVC32 | I_BIT | F_BIT
	MSR	cpsr, r1

#ifdef USE_LEDS_FOR_DEBUG
	LDR	r1, L$_IXM1200_LED_ADDR
	MOV	r2, #5
	STR	r2, [r1]
#endif /* USE_LEDS_FOR_DEBUG */

	/*
	 * Copy three instruction from copy_start2 to SRAM, and then
	 * execute from there during the MMU transition
	 */

	ADR	r1, copy_start2
	LDR	r4, L$_SRAM_COPY_ADDR
	LDMIA	r1, {r5,r6,r7}
	STMIA	r4, {r5,r6,r7}

	/* Load register constants first, so we have less to copy */

	MOV	r1, #MMU_INIT_VALUE
	MOV	r2, #0
	LDR	r3, L$_ROM_INIT_PLUS4

	/* Jump to SRAM to finish */

	MOV	pc, r4
copy_start2:

	/* Disable the MMU */

	MCR	CP_MMU, 0, r1, c1, c0, 0	/* Write to MMU CR */

	/* Flush I-cache */

	MCR	CP_MMU, 0, r2, c7, c7, 0	/* Flush (inval) all I,D-cache */

	/* jump to romInit + 4 */

	MOV	pc, r3

/*******************************************************************************
*
* sysWrite16 - explicitly perform a 16-bit write
*
* This routine simply performs a 16-bit write, i.e. an STRH instruction. This
* would be used for I/O peripherals where it is significant whether a
* store is an STR, STRB or STRH. This routine may be particularly
* useful when the behaviour of the C compiler is not appropriate.
*
* NOTE
* For reasons of efficiency, this routine does not establish a stack frame.
*
* RETURNS: N/A

* void sysWrite16
*	(
*	volatile UINT16 *	address,	/@ address to write to @/
*	UINT16			data		/@ data to write @/
*	)

*/

_ARM_FUNCTION_CALLED_FROM_C(sysWrite16)

	STRH	r1, [r0]	/* Store the 16-bit quantity */
	MOV	pc, lr		/* Return */

/*******************************************************************************
*
* sysRead16 - explicitly perform a 16-bit read
*
* This routine simply performs a 16-bit read, i.e. an LDRH instruction. This
* would be used for I/O peripherals where it is significant whether a store
* is an LDR, LDRB or LDRH.
*
* NOTE
* For reasons of efficiency, this routine does not establish a stack frame.
*
* RETURNS: the value read

* UINT16 sysRead16
*	(
*	volatile UINT16 *	address,	/@ address to read @/
*	)

*/

_ARM_FUNCTION_CALLED_FROM_C(sysRead16)

	LDRH	r0, [r0]	/* Load the 16-bit quantity */
	MOV	pc, lr		/* Return */


/*******************************************************************************
*
* swap32 - swap the bytes in a 32-bit word
*
* This routine swaps the bytes in a 32-bit word;  i.e. it would convert
* 0x12345678 to 0x78563412.
*
* NOTE
* For reasons of efficiency, this routine does not establish a stack frame.
*
* RETURNS: the swapped data
*
* UINT32 swap32
*	(
*	UINT32			data		/@ data to be swapped @/
*	)
*/

_ARM_FUNCTION_CALLED_FROM_C(swap32)

	/* Assume r0 initially contains 11223344 */
	AND	r1, r0, #0x0000FF00 /* r1 = 00003300 */
	MOV	r1, r1, lsl #8      /* r1 = 00330000 */
	ORR     r1, r1, r0, lsl #24 /* r1 = 44330000 */
	AND     r2, r0, #0x00FF0000 /* r2 = 00220000 */
	ORR	r1, r1, r2, lsr #8  /* r1 = 44332200 */
	ORR     r0, r1, r0, lsr #24 /* r0 = 44332211 */
	MOV	pc, lr		/* Return */


/*******************************************************************************
*
* swap16 - swap the bytes in a 16-bit word
*
* This routine swaps the bytes in a 16-bit word;  i.e. it would convert
* 0x1234 to 0x3412.
*
* NOTE
* For reasons of efficiency, this routine does not establish a stack frame.
*
* RETURNS: the swapped data
*
* UINT16 swap16
*	(
*	UINT16			data		/@ data to be swapped @/
*	)
*/

_ARM_FUNCTION_CALLED_FROM_C(swap16)

	/* Assume r0 initially contains xxxx1122 */
	MOV     r0, r0, lsl #16     /* r0 = 11220000 */
	MOV     r1, r0, lsl #8      /* r1 = 22000000 */
	ORR	r1, r1, r0, lsr #8  /* r1 = 22112200 */
	MOV	r0, r1, lsr #16     /* r0 = 00002211 */
	MOV	pc, lr		/* Return */


/*******************************************************************************
*
* pciCsrWr - Write PCI CSR register safely under C0 / Hyannis bug
*
* This routine writes a PCI CSR and then reads it back. This is to avoid a
* hardware bug in C0/Hyannis where if a write to a PCI CSR is followed by
* a PCI Mem/IO/Config write, a random CSR can get trashed.
*
* For safety, interrupts are disabled during this so that we can't be
* swapped out
*
* NOTE
* For reasons of efficiency, this routine does not establish a stack frame.
*
* RETURNS: N/A
*
* void pciCsrWr
*	(
*	void*			addr		/@ Address to be written @/
*	UINT32			data		/@ data to be written @/
*	)
*/

_ARM_FUNCTION_CALLED_FROM_C(pciCsrWr)
	/* Disable insterrupts */
	MRS	r2, cpsr
	ORR	r3, r2, #I_BIT | F_BIT
	MSR	cpsr, r3

	/* Do write */
	STR	r1, [r0]
	LDR	r1, [r0]

	/* Restore interrupts */
	MSR	cpsr, r2

	MOV	pc, lr		/* Return */

/*******************************************************************************
*
* getFP - Return the frame pointer of the caller of this routine
*
* This routine returns the frame pointer from the caller of this routine.
*
* RETURNS: the frame pointer

* UINT32 getFP(void)

*/
	.globl FUNC(getFP)
_ARM_FUNCTION_CALLED_FROM_C(getFP)
	MOV r0, fp
	LDR r0, [r0,#-12]
	MOV pc, lr

/******************************************************************************/

/*
 * PC-relative-addressable pointers - LDR Rn,=sym was (is?) broken
 * note "_" after "$" to stop preprocessor performing substitution
 */

	.balign	4

L$_vxSvcIntStackBase:
	.long	VAR(vxSvcIntStackBase)

L$_vxSvcIntStackEnd:
	.long	VAR(vxSvcIntStackEnd)

L$_vxIrqIntStackBase:
	.long	VAR(vxIrqIntStackBase)

L$_vxIrqIntStackEnd:
	.long	VAR(vxIrqIntStackEnd)

L$_IXM1200_PPL_CFG:
	.long IXM1200_PLL_CFG

L$_IXM1200_RESET:
	.long IXM1200_RESET

L$_IXM1200_SDRAM_CSR:
	.long IXM1200_SDRAM_CSR

	/* IXM1200_LED_ADDR is either in memory or is the same as GPIO_DATA */

L$_IXM1200_LED_ADDR:
	.long IXM1200_LED_ADDR

L$_SRAM_COPY_ADDR:
	.long SRAM_COPY_ADDR

	/*
	 * ROM_INIT_PLUS4 needs to be a physical address as we are turning
	 * the MMU off before we use it; so we must remove the
	 * ROM_VIRT_OFFSET
	 */

L$_ROM_INIT_PLUS4:
	.long (ROM_TEXT_ADRS + 4 - ROM_VIRT_OFFSET)

/*
 * Force the inclusion of ___ashldi3 in the BSP
 */

	.long FUNC(__ashldi3)