target.nr

vxworks的BSP开发配置文件

'\" t
.so wrs.an
.\" IXM1200/target.nr - Intel IXM1200 target specific documentation
.\"
.\" Copyright 2001 Intel Corporation
.\"
.\" modification history
.\" --------------------
.\" 01a,10jul02,scm  bspVal mods
.\" 01h,06feb02,j_b  note that compressed bootrom is not recommended for use
.\" 01g,16may01,jdg  modified for IXM1200 board
.\" 01f,23feb00,jdg  updated for Rev-E board
.\" 01e,28jan00,jdg  updated to match target.txt
.\" 01d,05Jan00,jdg  added support for Intel 82559
.\" 01c,27oct99,jdg  changed from A01 to B01 version
.\" 01b,13aug99,jdg  changed name from vbsa1200 to ixp1200eb
.\" 01a,10aug99,jdg  created, derived from ebsa285
.\"
.TH IXM1200 T "Intel IXM1200" "Rev: 16 MAY 01" "TORNADO REFERENCE: VXWORKS"

.SH "NAME"
.aX "Intel IXM1200"

.SH "INTRODUCTION"
This reference entry provides board-specific information necessary to
run VxWorks for the IXM1200 Network Processor Base Card (IXM1200). Before
using a board with VxWorks, verify that the board runs in the
factory configuration using vendor-supplied firmware and jumper
settings and checking the RS-232 and ethernet connections.


.SS "Boot ROMs"
The IXM1200 board uses one VxWorks boot ROMs (actually one
16-bit wide Intel TE28F320C3B90 Flash memory devices). Install it in
U23, with pin-1 nearer to the NetROM connector. For further
information, see the section "ROM Considerations" below.

The BSP does not have non-volatile RAM; however it uses part of
the Flash memory to save boot parameters. Thus, boot parameters are
preserved whenever the system is powered off.

To load VxWorks and for more information, follow the instructions
in the
.I "Tornado User's Guide: Getting Started."


.SS "Board/Chip revisions"

This document describes the production revision of the
board.

.SS "Jumpers"

The following switches are relevant to VxWorks configuration.

.TS E
expand;
cf3 s s
lf3 lf3 lf3
l l lw(3i) .
.ne 5
IXM1200
.sp .25
Switch	Function	Description
_
SW1	Reset	T{
Push to reset
T}
SW2	GPIO 0	T{
General Purpose I/O: Boot OS: ON=1 (1)
T}
SW2	GPIO 1	T{
General Purpose I/O: Boot OS: ON=1 (1)
T}
SW2	GPIO 2	T{
General Purpose I/O: ON=1
T}
SW2	GPIO 3	T{
General Purpose I/O: Flash Mode: ON=1 (should be 1 = 16-bit mode)
T}
SW2	FL/~NR	T{
Boot Mode: ON=Flash, OFF=NetROM
T}
.TE

For details of jumper configuration, see the board diagram at the
end of this entry and in the hardware manual.

(1) GPIO[1:0] determine which operating system is booted after
reset. Valid configurations are:

.TS E
expand;
cf3 s
lf3 lf3
l l .
.ne 5
Boot Options
.sp .25
GPIO[1:0]	OS
_
00	Diagnostics
01	Cygmon
10	VxWorks
11	Boot Manager
.TE

For more details, see the Section "ROM considerations".

.SH "FEATURES"
The IXM1200 is the base card for Intel's IXM1200
network processor. This provides an interface between the IXM1200,
SDRAM, SRAM, Flash ROM, Octal MAC, and a bridge to the primary PCI
bus. It also provides DMA controllers, timers, a serial port (UART),
and a PCI Bus arbiter.

The IXM1200 processor features six independent programming
MicroEngines for network data processing, and an F-Bus Interface.

The board supports 128 megabytes of SDRAM, 4 megabytes of SRAM, and
4 megabytes of Flash ROM.


.SH "SUPPORTED FEATURES"
The BSP is configured by default to configure the secondary PCI bus.


.SS "RAM size"
The BSP supports the default configuration of 128 MB SDRAM. Of
this, the upper 16 MB are remapped to virtual address 0 and are
available for use by VxWorks. The lower 112 MB are mapped to
0xC0000000 and are uncached. This may be changed by modifying the
BSP. For more details, see the "Cache/MMU considerations" section
below.

The BSP supports 4 MB of SRAM, although this is not included in
the VxWorks memory pool. Use of this memory must be managed by
application specific code.


.SS "Flash Memory"
A driver is provided supporting access to the Flash memory and the
use of a section of it as NVRAM.

The Flash may be updated using the Flash Utility (available through
the boot manager) and the host program FUTIL.EXE.


.SS "Timers"
The BSP uses hardware timers 2 and 3. Timers 1 and 4 are available
to application code.

The timestamp timer is timed to the system clock. This implies that 
you will not be able to enable/disable the timestamp timer, it is free 
running while the system clock is enabled. bspVal tests which 
enable/disable the timestamp timer will fail (and are expected too).


.SS "NetROM Support"
The BSP supports the use of NetROM in place of Flash
memory.


.SS "Unsupported Features"
No support is provided for the Real Time Clock. No use is made of
the following features, although there should be no reason why
they cannot be used:
.IP
    DMA Controllers,
.IP
    I20 Message unit,
.IP
    timers 1 and 4
.LP

The BSP provides no support for use of the MicroEngines or F-Bus
Interface.  This support is provided through application libraries.


.SH "HARDWARE DETAILS"
.SS "Devices"
The device drivers included are:

    1xm1200Timer.c - IXM1200 timer driver
    ixm1200Sio.c - IXM1200 UART serial driver
    ixm1200IntrCtl.c - IXM1200 interrupt controller driver
    flashMem.c - Flash memory (including 28F800) driver
    nullNvRam.c - NVRAM-to-Flash memory library
    pciIomapLib.c - PCI driver
    pciIomapShow.c - PCI Show routines
    sysEnd.c - Ethernet driver
    21555drv.c - Initialize 21555 Non-transparent bridge

See the manual entry for ixm1200Sio.c.


.SS "Shared Memory"
This BSP has not been tested with shared memory.  There is no
support provided for the use of the PCI mailbox/doorbell features
and there is no BSP-specific support for test-and-set
primitives.  The vxTas() primitive is provided in the
architecture-specific code to allow access to the ARM SWPB
instruction. For further information, see the vxTas() reference entry.


.SS "Interrupts"
This BSP only supports non-preemptive interrupt processing.  So
effectively there is only 1 interrupt level. 32 Interrupt vectors
are provided:
.TS E
expand;
c c c .
     0	reserved_00
     1	SI           	Soft interrupt
     2	reserved_02
     3	reserved_03
     4	T1           	Timer 1
     5	T2           	Timer 2
     6	T3           	Timer 3
     7	T4           	Timer 4
     8	reserved_08
     9	CINT         	CINT pin (IRQ)
    10	UENG         	Microengine (IRQ)
    11	SRAM         	SRAM unit (IRQ)
    12	UART         	UART unit (IRQ)
    13	SDRAM        	SDRAM unit (IRQ)
    14	RTC          	Real Time Clock: Currently Unused
    15	DFH          	Doorbell from host
    16	DMA1         	DMA channel 1
    17	DMA2         	DMA channel 2
    18	PIL          	pci_irq_l
    19	reserved_19
    20	DMA1NB       	DMA1 not busy
    21	DMA2NB       	DMA2 not busy
    22	SB           	Start BIST
    23	RSERR        	Received SERR
    24	SDPAR        	SDRAM parity
    25	IIP          	I20 inbound post_list
    26	reserved_26
    27	DTE          	Discard Timer Expired
    28	DPED         	Data Parity Error Detected
    29	RMA          	Received Master Abort
    30	RTA          	Received Target Abort
    31	DPE          	Detect Parity Error
.TE

Only interrupt vectors 5, 6, 12, and 18 are used by default in
this BSP.

Interrupt connection, enabling, and disabling are performed using
the standard intArchLib routines. Interrupts 9 through 14
(inclusive) cannot be enabled or disabled using the standard
routines. These must be enabled or disabled by writing to the
appropriate control register directly. The interrupt controller
driver is provided in ixm1200IntrCtl.c.


.SS "Serial Configuration"
There is one serial port on the board.  This connector is located
on the bulkhead (edge of the card away from the PCI connector).
The port is "data leads only", that is, there are no
handshake lines provided at all. The default configuration is 9600
baud, 8 data bits, no parity, 1 stop bit.


.SS "SCSI Configuration"
This BSP does not support SCSI.


.SS "Network Configuration"
A network interface is provided by an Intel 82559 Ethernet controller
on the secondary PCI bus. The interface is
called "eeE" and should be specified as the boot device to the boot
ROMs. The Ethernet MAC address is read from the PCI