ixm1200.h

vxworks的BSP开发配置文件

#define AMBA_TIMER_BASE		0x42000300	/* Address of base of timer */

#define AMBA_TIMER_SYS_TC_DISABLE	(TC_DISABLE | TC_PERIODIC)
#define AMBA_TIMER_SYS_TC_ENABLE	(TC_ENABLE  | TC_PERIODIC)
#define AMBA_TIMER_AUX_TC_DISABLE	(TC_DISABLE | TC_PERIODIC)
#define AMBA_TIMER_AUX_TC_ENABLE	(TC_ENABLE  | TC_PERIODIC)

#define SYS_TIMER_CLK_DEFAULT	 	(199070000)	/* Frequency of counter/timer*/
#define AUX_TIMER_CLK_DEFAULT		(199070000) /* Frequency of counter/timer*/
#define SYS_TIMER_CLK_A             (176950000)
#define SYS_TIMER_CLK_C             (232240000)

#if 0  /* Set timer speed based on Chip Rev, assume "not less than 1" */
#define SYS_TIMER_CLK               SYS_TIMER_CLK_A /* Frequency of counter/timer*/
#define AUX_TIMER_CLK               SYS_TIMER_CLK_A /* Frequency of counter/timer*/
#else
#define SYS_TIMER_CLK               SYS_TIMER_CLK_DEFAULT /* Frequency of counter/timer*/
#define AUX_TIMER_CLK               SYS_TIMER_CLK_DEFAULT /* Frequency of counter/timer*/
#endif

#define AMBA_RELOAD_TICKS	0		/* no overhead reloading timer*/

#define SYS_TIMER_CLEAR(x)	(AMBA_TIMER_T3CLEAR(x)) /* sys Clk is timer 1 */
#define SYS_TIMER_CTRL(x)	(AMBA_TIMER_T3CTRL(x))
#define SYS_TIMER_LOAD(x)	(AMBA_TIMER_T3LOAD(x))
#define SYS_TIMER_VALUE(x)	(AMBA_TIMER_T3VALUE(x))
#define AUX_TIMER_CLEAR(x)	(AMBA_TIMER_T2CLEAR(x)) /* aux Clk is timer 2 */
#define AUX_TIMER_CTRL(x)	(AMBA_TIMER_T2CTRL(x))
#define AUX_TIMER_LOAD(x)	(AMBA_TIMER_T2LOAD(x))
#define AUX_TIMER_VALUE(x)	(AMBA_TIMER_T2VALUE(x))

#define SYS_TIMER_INT_LVL 	(INT_VEC_T3)
#define AUX_TIMER_INT_LVL	(INT_VEC_T2)

/* Definitions for driving LED on board */

#define LED_MEM_MAPPED

#ifdef LED_MEM_MAPPED
#define IXM1200_LED_ADDR   (0x38400000+0x108000)  /* Address of LED display */
#else
#define IXM1200_LED_ADDR   IXM1200_GPIO_DATA
#endif

/*
 * Maximum clock rates depend upon CPU power and work load of application.
 * They will also critically depend on whether caches are enabled.
 * The values below are minimum and maximum allowed by the hardware/software.
 * The counter is 24-bit and we don't accept values that would mean a zero
 * reload value as we don't know what that will do.
 * So:
 * min frequency = roundup(clock_rate/(max_counter_value))
 * max frequency = rounddown(clock_rate/(min_counter_value))
 * i.e. SYS_CLK_RATE_MAX = SYS_TIMER_CLK
 *      AUX_CLK_RATE_MAX = AUX_TIMER_CLK
 *
 * However, we must set maxima that are sustainable on a running
 * system. The values below have been chosen so that there is a
 * reasonable margin and the BSP passes the test suite.
 */

#define SYS_CLK_RATE_MIN ((SYS_TIMER_CLK+0xFFFFFF)/0x1000000)
#define AUX_CLK_RATE_MIN ((AUX_TIMER_CLK+0xFFFFFF)/0x1000000)
#define SYS_CLK_RATE_MAX 60000
#define AUX_CLK_RATE_MAX 60000

/* Flash memory configuration - see config.h for more details */

#ifdef INCLUDE_FLASH
#define FLASH_WIDTH     4		/* 32-bit wide (two 16-bit wide parts)*/
#endif /* INCLUDE_FLASH */

/* GPIO registers control bit values */

#define GPIO_OWN_CCCC    (0<<4)        /* Core owns all GPIO */
#define GPIO_OWN_CCCF    (1<<4)        /* Fbi owns GPIO[0] */
#define GPIO_OWN_FFFC    (2<<4)        /* Fbi owns GPIO[3:1] */
#define GPIO_OWN_FFFF    (3<<4)        /* Fbi owns GPIO[3:0] */
#define GPIO_OUTPUT(mask) (mask)       /* Which GPIO's are outputs */

#ifdef INCLUDE_PCI
/*
 * PCI definitions
 *
 * First, defines for generic pciIoMapLib.c code
 *
 * Cache Line Size - in number of 32-bit words
 * It might be thought that we would set this to (_CACHE_ALIGN_SIZE/4), but,
 * in fact, the areas of memory mapped for use either by PCI I/O and
 * PCI Configuration  and the area of (ARM) memory used by the Ethernet
 * controller are marked as non-cacheable, so we should set it to zero.
 */

#define PCI_CLINE_SZ    0

/*
 * Latency Timer value
 * A sensible value for this depends what we are using PCI for.
 * (Rather arbitrarily) leave it at 0 (the reset default value)
 */

#define PCI_LAT_TIMER           0x0


#define SWAP16(x) ((((x) << 8) | ((x) >> 8)) & 0xFFFF)
#define SWAP32(x)               \
  (((x) << 24) |                \
  (((x) & 0x0000FF00) << 8) |   \
  (((x) & 0x00FF0000) >> 8) |   \
  (((unsigned int)(x)) >> 24))

#if (_BYTE_ORDER == _BIG_ENDIAN)
#define SWAP32PCIFUNC(x) (swap32(x))
#define SWAP16PCIFUNC(x) (swap16(x))
#define SWAP32PCI(x)     (SWAP32(x))
#else
#define SWAP32PCIFUNC(x) (x)
#define SWAP16PCIFUNC(x) (x)
#define SWAP32PCI(x)     (x)
#endif

#define PCI_IN_BYTE(x)      *(UINT8 *) (x)
#define PCI_IN_WORD(x)      (SWAP16PCIFUNC(sysRead16((UINT16 *)(x))))
#define PCI_IN_LONG(x)      (SWAP32PCIFUNC(*(UINT32 *)(x)))
#define PCI_OUT_BYTE(x,y)   *(UINT8 *) (x) = (UINT8)  y
#define PCI_OUT_WORD(x,y)   sysWrite16((UINT16 *)(x), SWAP16PCIFUNC((UINT16)(y)))
#define PCI_OUT_LONG(x,y)   *(UINT32 *)(x) = SWAP32PCIFUNC((UINT32) (y))


/*
 * Dummy interrupt number for pciIntConnect(): must be passed a real
 * interrupt vector number. This allows for non-linear mappings
 * between interrupts, slots etc.
 */

#define INT_NUM_IRQ0    0


/* memory map as seen by the CPU on the local bus */
#ifdef INCLUDE_EXTRA_PCI_MAPPING
#define CPU_PCI_MEM_ADRS    PCI_MEM_BASE /* PCI memory space base */
#define CPU_PCI_MEM_SIZE    0x08000000   /* 128 Mbytes */
#endif

#define CPU_PCI_IO_ADRS     PCI_IO_BASE  /* PCI I/O space base */
#define CPU_PCI_IO_SIZE     0x00010000   /* 64 kbytes */

#define CPU_PCI_CNFG_ADRS   PCI_CONFIG0_BASE  /* type 0 PCI config space */
#define CPU_PCI_CNFG_SIZE   0x00C00000        /* 12 Mbytes */

#define CPU_PCI_CNFG_1_ADRS PCI_CONFIG1_BASE  /* type 1 PCI config space */
#define CPU_PCI_CNFG_1_SIZE 0x01000000        /* 16 Mbytes */


/* PCI view of PCI I/O space for PCI devices */

#define PCI_IO_ADRS         0x00000000  /* base of PCI I/O address */

/* This is where physical SDRAM[0] appears on PCI bus */
#define PCI2DRAM_BASE_ADRS  0x00000000  /* memory seen from PCI bus */


/* PCI bus resources */

#define PCI_IO_SIZE     0x80            /* PCI I/O size */

/* PCI device 0: slot I/O 4 */

#define PCI_MEM_ADR0            0x00            /* Memory base for CSR */
#define PCI_IO_ADR0             PCI_IO_ADRS     /* I/O base for CSR 32Bytes */
#define PCI_IO_SIZE0            PCI_IO_SIZE     /* I/O size for CSR */
#define PCI_INT_LVL0            INT_VEC_PIL     /* Interrupt level */
#define PCI_INT_VEC0            IVEC_TO_INUM(PCI_INT_LVL0) /* Interrupt vector */

/* PCI device 1: slot I/O 3 */

#define PCI_MEM_ADR1            0x00
#define PCI_IO_ADR1             PCI_IO_ADRS
#define PCI_IO_SIZE1            PCI_IO_SIZE
#define PCI_INT_LVL1            INT_VEC_PIL
#define PCI_INT_VEC1            IVEC_TO_INUM(PCI_INT_LVL1)

/* PCI device 2: slot I/O 2 */

#define PCI_MEM_ADR2            0x00
#define PCI_IO_ADR2             PCI_IO_ADRS
#define PCI_IO_SIZE2            PCI_IO_SIZE
#define PCI_INT_LVL2            INT_VEC_PIL
#define PCI_INT_VEC2            IVEC_TO_INUM(PCI_INT_LVL2)

/* PCI device 3: slot I/O 1 */

#define PCI_MEM_ADR3            0x00
#define PCI_IO_ADR3             PCI_IO_ADRS
#define PCI_IO_SIZE3            PCI_IO_SIZE
#define PCI_INT_LVL3            INT_VEC_PIL
#define PCI_INT_VEC3            IVEC_TO_INUM(PCI_INT_LVL3)

/*
 * N.B. Only the following values have been tested. In particular, no
 * testing has been performed with more than one PCI bus, i.e. Type 1
 * configuration.
*/

#define PCI_MAX_DEV    12
#define PCI_MAX_BUS     1       /* Only one bus */


/* Allocate Device Space (Offsets) for PCI devices */

#define LAN_DEV_SPACE       0
#define PCI_IO_LN_ADRS      (PCI_IO_ADRS + LAN_DEV_SPACE)


/* Allocated base address of h/w devices as seen from CPU */

#define LAN_BASE_ADRS       (CPU_PCI_IO_ADRS + LAN_DEV_SPACE)


/* Create configuration address */

#define MAKE_CFG_ADDR(bus, device, func, offset) ((bus) ? \
    ((UINT32)((bus & 0xFF) << 16) | (UINT32)((device & 0x1F) << 11) | \
     (UINT32)((func & 0x7) << 8)  | 0x01) : \
    ((UINT32)(1 << ((device & 0x0F) + 11)) | (UINT32)((func & 0x7) << 8) | \
     (UINT32) (offset & 0xFC)))

#endif /* ifdef INCLUDE_PCI */


/* Define Bridge subsystem IDs */
#define SI_VEND_ID 0x8086
#define SI_SYS_ID  0x10AB
#define BV_SYS_ID  0x1104
#define DC_SYS_ID  0x1120

/* Defines the corresponding CSR Base sizes */
#define IXM1200_PCI_MEM_BAR_SIZE        0x00100000                      /* 1 Meg: CSR Mem Base */
#define IXM1200_PCI_IO_BAR_SIZE         0x00000080                      /* 128: CSR I/O Base */

#ifdef __cplusplus
}
#endif

#endif	/* INCixm1200h */