ixm1200.h

vxworks的BSP开发配置文件

                   (SDRAM_INIT))

#define SDRAM_EN_INT_BIT   10
#define SDRAM_EN_ECC_BIT    3

/* Memory space definition */

#define FLASH_PHYS_BASE   0x00000000 /* Physical address of start of FLASH */

#define SRAM_BASE         0x10000000 /* Base of SRAM R/W area */
#define SRAM_RL_BASE      0x12000000 /* Read-lock area */
#define SRAM_WU_BASE      0x14000000 /* Write-unlock area */
#define SRAM_CU_BASE      0x16000000 /* CAM Unlock area */
#define SRAM_BWC_BASE     0x18000000 /* Bit-Write-Clear area */
#define SRAM_BWS_BASE     0x18800000 /* Bit-Write-Set area */
#define SRAM_BTC_BASE     0x19000000 /* Bit Test & Clear area */
#define SRAM_BTS_BASE     0x19800000 /* Bit Test & Set area */
#define SRAM_PUSH_BASE    0x20000000 /* Push command area */
#define SRAM_PUSH_BASE_Q0 0x20000000 /* Push command area: queue 0 */
#define SRAM_PUSH_BASE_Q1 0x20800000 /* Push command area: queue 1 */
#define SRAM_PUSH_BASE_Q2 0x21000000 /* Push command area: queue 2 */
#define SRAM_PUSH_BASE_Q3 0x21800000 /* Push command area: queue 3 */
#define SRAM_PUSH_BASE_Q4 0x22000000 /* Push command area: queue 4 */
#define SRAM_PUSH_BASE_Q5 0x22800000 /* Push command area: queue 5 */
#define SRAM_PUSH_BASE_Q6 0x23000000 /* Push command area: queue 6 */
#define SRAM_PUSH_BASE_Q7 0x23800000 /* Push command area: queue 7 */
#define SRAM_POP_BASE     0x24000000 /* Pop command area */
#define SRAM_POP_BASE_Q0  0x24000000 /* Pop command area: queue 0 */
#define SRAM_POP_BASE_Q1  0x24800000 /* Pop command area: queue 1 */
#define SRAM_POP_BASE_Q2  0x25000000 /* Pop command area: queue 2 */
#define SRAM_POP_BASE_Q3  0x25800000 /* Pop command area: queue 3 */
#define SRAM_POP_BASE_Q4  0x26000000 /* Pop command area: queue 4 */
#define SRAM_POP_BASE_Q5  0x26800000 /* Pop command area: queue 5 */
#define SRAM_POP_BASE_Q6  0x27000000 /* Pop command area: queue 6 */
#define SRAM_POP_BASE_Q7  0x27800000 /* Pop command area: queue 7 */
#define SRAM_CSR_BASE     0x38000000 /* SRAM CSRs */
#define IXM1200_SRAM_CSR          0x38000000 /* SRAM CSR */
#define IXM1200_SRAM_SLOW_CONFIG  0x38000020 /* SRAM Flash/Mac cycle times */
#define IXM1200_SRAM_FLASH_CONFIG 0x38000024 /* Flash timing */
#define IXM1200_SRAM_MAC_CONFIG   0x38000028 /* Mac timing */
#define SRAM_IO_BASE      0x38400000 /* Async I/O (MAC) space */

#define PCI_CSR_BASE      0x42000000 /* Local config / CSR space */
#define PCI_CONFIG1_BASE  0x52000000 /* Config cycle 1 space */
#define PCI_CONFIG0_BASE  0x53000000 /* Config cycle 0 space */
#define PCI_IO_BASE       0x54000000 /* I/O cycle space */
#define PCI_MEM_BASE      0x60000000 /* Mem cycle space */

#define IXM1200_SYS_REG_BASE 0x90000000 /* Base of IXM1200 System registers */
#define IXM1200_PLL_CFG      0x90000C00 /* PLL Configuration Reg */
#define IXM1200_FIQ          0x90001000 /* FIQ interrupt register */
#define IXM1200_IRQ          0x90001400 /* IRQ interrupt register */
#define IXM1200_GPIO_EN      0x90001800 /* Address of GPIO_EN register */
#define IXM1200_GPIO_DATA    0x90001C00 /* Address of GPIO_DATA register */
#define IXM1200_RTC_DIV      0x90002000 /* Real Time Clock Divider & Int enable */
#define IXM1200_UART_CR      0x90003800 /* UART Control Register */
#define IXM1200_SYS_REG_SIZE 0x00003C00

/*
 * Area used to flush caches.
 * HW area that doesn't cause AMBA transactions
 */
#define CACHE_FLUSH_BASE 0xA0000000 /* Cache Flush area */
#define MINICACHE_FLUSH_BASE  (CACHE_FLUSH_BASE + 0x00100000)

#define UENG_CSR_BASE    0xB0000000 /* MicroEngine CSR Base */
#define UENG_CSR_SIZE    0x00003000 /* MicroEngine CSR size */
#define UENG_XFER_BASE   0xB0004000 /* MicroEngine Xfer Reg Base */
#define UENG_XFER_SIZE   0x00003000 /* MicroEngine Xfer Reg size */

#define FBI_CSR_BASE     0xB0040000 /* FBI CSR Base, size == 1 page */
#define IXM1200_IREG      0xB00401E0 /* FBI Interrupt Register: IREG */

#define FBI_SCRATCH_BASE 0xB0044000 /* Scratchpad Base */
#define FBI_SCRATCH_SIZE 0x00001000 /* Scratchpad size */

#define SDRAM_PHYS_BASE  0xC0000000 /* Physical address of start of SDRAM */
#define SDRAM_PF_BASE    0xD0000000 /* SDRAM Pre-Fetch Base */
#define SDRAM_CSR_BASE   0xFF000000 /* SDRAM CSR Base */
#define IXM1200_SDRAM_CSR     0xFF000000 /* SDRAM CSR */
#define IXM1200_SDRAM_MEMCTL0 0xFF000004 /* SDRAM timing info */
#define IXM1200_SDRAM_MEMCTL1 0xFF000008 /* SDRAM timing info */
#define IXM1200_SDRAM_MEMINIT 0xFF00000C /* SDRAM initialization timing */

/*
 * SDRAM_VIRT_OFFSET is the physical address of SDRAM corresponding
 * to virtual address 0
 */

#define SDRAM_VIRT_OFFSET (SDRAM_PHYS_BASE + RESERVED_LOW_MEM)

/*
 * PCI REGISTERS
 */

/* PCI Reset register control bit values*/

#define RESET_MICROENGINE   0x0000003F   /* Reset 6 microengines */
#define RESET_EXTERNAL      0x00008000   /* External interrupt (output) */
#define RESET_FULL          0xFFFFFFFF   /* Full chip reset */

/* Interrupt addresses */

#define IXM1200_IRQSTATUS      0x42000180 /* IRQ Status */
#define IXM1200_IRQRAWSTATUS   0x42000184 /* IRQ Raw Status */
#define IXM1200_IRQENABLE      0x42000188 /* IRQ Enable R/O */
#define IXM1200_IRQENABLE_SET  IXM1200_IRQENABLE /* IRQ Enable set W/O */
#define IXM1200_IRQENABLECLEAR 0x4200018C /* IRQ Enable clear */
#define IXM1200_IRQ_SOFT       0X42000190

#define IXM1200_FIQSTATUS      0x42000280 /* FIQ Status */
#define IXM1200_FIQRAWSTATUS   0x42000284 /* FIQ Raw Status */
#define IXM1200_FIQENABLE      0x42000288 /* FIQ Enable R/O */
#define IXM1200_FIQENABLE_SET  IXM1200_FIQENABLE /* FIQ Enable set W/O */
#define IXM1200_FIQENABLECLEAR 0x4200028C /* FIQ Enable clear */
#define IXM1200_FIQ_SOFT       0X42000290

#define IXM1200_PCI_CSR_BASE 0x42000000 /* Base of PCI Unit CSR's */

#define IXM1200_PCI_VENDOR_ID  FIX_ADDR_16(IXM1200_PCI_CSR_BASE + 0x000)
#define IXM1200_PCI_DEVICE_ID  FIX_ADDR_16(IXM1200_PCI_CSR_BASE + 0x002)
#define IXM1200_PCI_MEM_BAR           (IXM1200_PCI_CSR_BASE + 0x010)
#define IXM1200_PCI_IO_BAR            (IXM1200_PCI_CSR_BASE + 0x014)
#define IXM1200_PCI_DRAM_BAR          (IXM1200_PCI_CSR_BASE + 0x018)
#define IXM1200_OUTB_INT_STATUS       (IXM1200_PCI_CSR_BASE + 0x030)
#define IXM1200_OUTB_INT_MASK         (IXM1200_PCI_CSR_BASE + 0x034)
#define IXM1200_PCI_INT_LAT           (IXM1200_PCI_CSR_BASE + 0x03c)
#define IXM1200_I20_INB_FIFO          (IXM1200_PCI_CSR_BASE + 0x040)
#define IXM1200_I20_OUTB_FIFO         (IXM1200_PCI_CSR_BASE + 0x044)
#define IXM1200_MAILBOX0              (IXM1200_PCI_CSR_BASE + 0x050)
#define IXM1200_MAILBOX1              (IXM1200_PCI_CSR_BASE + 0x054)
#define IXM1200_MAILBOX2              (IXM1200_PCI_CSR_BASE + 0x058)
#define IXM1200_MAILBOX3              (IXM1200_PCI_CSR_BASE + 0x05c)
#define IXM1200_DOORBELL              (IXM1200_PCI_CSR_BASE + 0x060)
#define IXM1200_DOORBELL_SETUP        (IXM1200_PCI_CSR_BASE + 0x064)
#define IXM1200_CAP_PTR_EXT           (IXM1200_PCI_CSR_BASE + 0x070)
#define IXM1200_PWR_MGMT              (IXM1200_PCI_CSR_BASE + 0x074)
#define IXM1200_RESET                 (IXM1200_PCI_CSR_BASE + 0x07C)
#define IXM1200_CHAN_1_BYTE_COUNT     (IXM1200_PCI_CSR_BASE + 0x080)
#define IXM1200_CHAN_1_PCI_BAR        (IXM1200_PCI_CSR_BASE + 0x084)
#define IXM1200_CHAN_1_DRAM_ADDR      (IXM1200_PCI_CSR_BASE + 0x088)
#define IXM1200_CHAN_1_DESC_PTR       (IXM1200_PCI_CSR_BASE + 0x08C)
#define IXM1200_CHAN_1_CONTROL        (IXM1200_PCI_CSR_BASE + 0x090)
#define IXM1200_DMA_INF_MODE          (IXM1200_PCI_CSR_BASE + 0x09C)
#define IXM1200_CHAN_2_BYTE_COUNT     (IXM1200_PCI_CSR_BASE + 0x0A0)
#define IXM1200_CHAN_2_PCI_BAR        (IXM1200_PCI_CSR_BASE + 0x0A4)
#define IXM1200_CHAN_2_DRAM_ADDR      (IXM1200_PCI_CSR_BASE + 0x0A8)
#define IXM1200_CHAN_2_DESC_PTR       (IXM1200_PCI_CSR_BASE + 0x0AC)
#define IXM1200_CHAN_2_CONTROL        (IXM1200_PCI_CSR_BASE + 0x0B0)
#define IXM1200_CSR_BASE_ADDR_MASK    (IXM1200_PCI_CSR_BASE + 0x0F8)
#define IXM1200_DRAM_BASE_ADDR_MASK   (IXM1200_PCI_CSR_BASE + 0x100)
#define IXM1200_I20_INB_FLIST_HPTR    (IXM1200_PCI_CSR_BASE + 0x120)
#define IXM1200_I20_INB_PLIST_TPTR    (IXM1200_PCI_CSR_BASE + 0x124)
#define IXM1200_I20_OUTB_PLIST_HPTR   (IXM1200_PCI_CSR_BASE + 0x128)
#define IXM1200_I20_OUTB_FLIST_TPTR   (IXM1200_PCI_CSR_BASE + 0x12C)
#define IXM1200_I20_INB_FLIST_CNT     (IXM1200_PCI_CSR_BASE + 0x130)
#define IXM1200_I20_OUTB_PLIST_CNT    (IXM1200_PCI_CSR_BASE + 0x134)
#define IXM1200_I20_INB_PLIST_CNT     (IXM1200_PCI_CSR_BASE + 0x138)
#define IXM1200_SA_CONTROL            (IXM1200_PCI_CSR_BASE + 0x13C)
#define IXM1200_PCI_ADDR_EXT          (IXM1200_PCI_CSR_BASE + 0x140)
#define IXM1200_PREFETCH_RANGE        (IXM1200_PCI_CSR_BASE + 0x144)
#define IXM1200_DBELL_PCI_MASK        (IXM1200_PCI_CSR_BASE + 0x150)
#define IXM1200_DBELL_SA_MASK         (IXM1200_PCI_CSR_BASE + 0x154)

#define IXM1200_SA_CONTROL_BEO (1 << 18) /* PCI Big Endian Byte Enable Out */
#define IXM1200_SA_CONTROL_DEO (1 << 17) /* PCI Big Endian Data Enable Out */
#define IXM1200_SA_CONTROL_BEI (1 << 16) /* PCI Big Endian Byte Enable In */
#define IXM1200_SA_CONTROL_DEI (1 << 15) /* PCI Big Endian Data Enable In */

#define IXM1200_SA_CONTROL_PNR (1 << 9)  /* PCI Not Reset bit of SA_CONTROL */
#define IXM1200_SA_CONTROL_PCF (1 << 31) /* PCI Centrl Function bit */

/* 16 bit PCI registers */

#define IXM1200_PCI_COMMAND FIX_ADDR_16(IXM1200_PCI_CSR_BASE + 0x04)

/* Define PCI_COMMAND bits */

#define IXM1200_PCI_COMMAND_IOSE (1 << 0) /* I/O Space Enable */
#define IXM1200_PCI_COMMAND_MSE  (1 << 1) /* Mem Space Enable */
#define IXM1200_PCI_COMMAND_ME   (1 << 2) /* Master Enable */
#define IXM1200_PCI_COMMAND_MWI  (1 << 4) /* Master Write And Invalidate Enable */
#define IXM1200_PCI_COMMAND_PEC  (1 << 6) /* Parity Error Control */
#define IXM1200_PCI_COMMAND_SE   (1 << 8) /* SERR# enable */

/*
 * Interrupt Controller definitions
 */

#define IXM1200_INT_NUM_LEVELS	 1
#define IXM1200_INT_NUM_VECTORS  32

#define INT_VEC_DPE           31	/* Detect Parity Error */
#define INT_VEC_RTA           30	/* Received Target Abort */
#define INT_VEC_RMA           29	/* Received Master Abort */
#define INT_VEC_DPED          28	/* Data Parity Error Detected */

#define INT_VEC_DTE           27	/* Discard Timer Expired */
#define INT_VEC_reserved_26   26
#define INT_VEC_IIP           25	/* I20 inbound post_list */
#define INT_VEC_SDPAR         24	/* SDRAM parity */

#define INT_VEC_RSERR         23	/* Received SERR */
#define INT_VEC_SB            22	/* Start BIST */
#define INT_VEC_DMA2NB        21	/* DMA2 not busy */
#define INT_VEC_DMA1NB        20	/* DMA1 not busy */

#define INT_VEC_reserved_19   19
#define INT_VEC_PIL           18	/* pci_irq_l */
#define INT_VEC_DMA2          17	/* DMA channel 2 */
#define INT_VEC_DMA1          16	/* DMA channel 1 */

#define INT_VEC_DFH           15	/* Doorbell from host */
#define INT_VEC_UART          14	/* UART unit IRQ */
#define INT_VEC_SDRAM         13	/* SDRAM unit IRQ */
#define INT_VEC_RTC           12    /* Real Time Clock */

#define INT_VEC_SRAM          11	/* SRAM unit IRQ */
#define INT_VEC_UENG          10	/* Microengine IRQ */
#define INT_VEC_CINT           9	/* CINT pin IRQ */
#define INT_VEC_reserved_08    8

#define INT_VEC_T4             7	/* Timer 4 */
#define INT_VEC_T3             6	/* Timer 3 */
#define INT_VEC_T2             5	/* Timer 2 */
#define INT_VEC_T1             4	/* Timer 1 */

#define INT_VEC_reserved_03    3
#define INT_VEC_reserved_02    2
#define INT_VEC_SI             1	/* Soft interrupt */
#define INT_VEC_reserved_00    0

#define IXM1200_INT_CTRL_MASK 0xFBF780F2  /* Interrupts controllable from */
                                         /* the PCI registers */

/* definitions for IXM1200 UART */

#define UART_XTAL_FREQ                3686400    /* UART baud rate clock freq */
#define N_UART_CHANNELS               1          /* Total number UART channels */
#define N_SIO_CHANNELS         (N_UART_CHANNELS) /* Total number SIO channels */
#define N_IXM1200_UART_CHANNELS (N_UART_CHANNELS) /* Total number IXM1200 chan */

/*
 * Definitions for the AMBA Timer:
 * There are four timers. Timer four can be used as a watchdog. We will use
 * Timer-1 for the system clock, Timer-2 for the aux clock, and Timer-3 for
 * the timer stamp clock. The clocks are run from the system clock, not
 * divided.
 */