ixm1200.h

vxworks的BSP开发配置文件

/* ixm1200.h - Intel's ixm1200 board header */

/* Copyright 1998 Wind River Systems, Inc.; Copyright 1999 Intel Corp. */

/*
modification history
--------------------
01h,10jul02,scm  add C++ protection...
01g,10jul02,scm  bspVal mod: change sys_timer_clk so pkLib could be built
                 correctly...
01f,12sep01,scm  Define the corresponding CSR Base sizes...
01e,30aug01,scm  adjust to reflect ixm1200...
01d,06Oct00,jdg  Added Big-Endian support
01c,07Mar00,jdg  Added support for B0 revision ixp1200
01b,13aug99,jdg  changed name from vbsa1200 to ixp1200eb
01a,08apr99,jdg  created from 01e of brutus
*/

/*
 * This file contains I/O address and related constants for the
 * Intel ixm1200 board.
 */

#ifndef	INCixm1200h
#define	INCixm1200h

#ifdef __cplusplus
extern "C" {
#endif

/* General Purpose 32-bit register read/write macros */

#define IXM1200_REG_READ(a,val) ((val) = *(volatile UINT32 *)(a))
#define IXM1200_REG_WRITE(a,val) (*(volatile UINT32 *)(a) = (val))
#define IXM1200_PCI_REG_WRITE(a,val) pciCsrWr((void*)(a),(val))


#define TARGET_IXM1200

#define BUS		BUS_TYPE_PCI

/* Define macros for fixing 8 and 16 bit addresses for big-endian operation */
#if (_BYTE_ORDER == _BIG_ENDIAN)
#define FIX_ADDR_16(x) ((x) ^ 2)
#define FIX_ADDR_32(x) ((x) ^ 3)
#else
#define FIX_ADDR_16(x) (x)
#define FIX_ADDR_32(x) (x)
#endif

/*
 * Local-to-Bus memory address constants:
 * the local memory address always appears at 0 locally;
 * it is not dual ported.
 */

#define LOCAL_MEM_LOCAL_ADRS    0x00000000      /* fixed */
#define LOCAL_MEM_BUS_ADRS      0x00000000      /* fixed */

/* PLL Config */

/*
 * Values for Core Clock Configuration: all values assume that the PLL
 * is fed by a 3.6864 MHZ crystal oscillator.
 *
 * NOTE: changing the value used for the core clock speed means that
 * the other configuration parameters that specify timings in terms of
 * units of the core clock, e.g. the memory timings, may also need to be
 * changed.
 */

#define CCF_29_49   0
#define CCF_36_87   1
#define CCF_44_24   2
#define CCF_51_61   3
#define CCF_58_98   4
#define CCF_66_36   5
#define CCF_73_73   6
#define CCF_81_10   7
#define CCF_88_48   8
#define CCF_95_85   9
#define CCF_103_22 10
#define CCF_110_59 11
#define CCF_132_71 12
#define CCF_147_46 13
#define CCF_154_83 14
#define CCF_162_20 15
#define CCF_165_89 16
#define CCF_176_95 17
#define CCF_191_69 18
#define CCF_199_07 19

#define CCF_206_44 20
#define CCF_221_18 21
#define CCF_232_24 22

/* Real Time Clock control bits */

#define RTCDIV_IRQS (1 << 19) /* Interrupt sent on IRQ */
#define RTCDIV_IRST (1 << 18) /* Interrupt reset bit */
#define RTCDIV_IEN  (1 << 17) /* Interrupt Enable bit */
#define RTCDIV_WEN  (1 << 16) /* Write enable: 1 -> only write bits 17:19 */

#define RTCDIV_RESET_VAL (RTCDIV_WEN)

/************************************************************************/
/* IXM1200 supports:                                                    */
/* <= C0 (rev 3): 200 MHz                                               */
/* >  C0 (rev 3): 232 MHz                                               */
/************************************************************************/

#    define SRAM_8MSR 0 /* 8MB SRAM */
#    define SRAM_4MSR 1 /* 4MB SRAM */
#    define SRAM_2MSR 0 /* 2MB SRAM */

    /* SRAM Cycle times for flash/mac (based on 199/232 MHz clock) */

#    define SRAM_FCT_200 0x18 /* Flash cycle time */
#    define SRAM_MCT_200 0x59 /* Mac cycle time */

#    define SRAM_FCT_232 0x23 /* Flash cycle time */
#    define SRAM_MCT_232 0x59 /* Mac cycle time */

#    define SRAM_SLOW_CFG_200 ((SRAM_FCT_200 <<  8) | (SRAM_MCT_200))
#    define SRAM_SLOW_CFG_232 ((SRAM_FCT_232 <<  8) | (SRAM_MCT_232))

    /* SRAM Flash timing (based on 199/232 MHz clock) */

#    define SRAM_FRWA_200 0x18 /* Flash R/W Assert */
#    define SRAM_FEA_200  0x18 /* Flash Enable Assert */
#    define SRAM_FRWD_200 0x04 /* Flash R/W Deassert */
#    define SRAM_FED_200  0x00 /* Flash Enable Deassert */

#    define SRAM_FRWA_232 0x21 /* Flash R/W Assert */
#    define SRAM_FEA_232  0x1F /* Flash Enable Assert */
#    define SRAM_FRWD_232 0x06 /* Flash R/W Deassert */
#    define SRAM_FED_232  0x00 /* Flash Enable Deassert */

#    define SRAM_FLASH_CFG_200 ((SRAM_FRWA_200 << 24) | (SRAM_FRWD_200 <<  8) | \
                                (SRAM_FEA_200  << 16) | (SRAM_FED_200))
#    define SRAM_FLASH_CFG_232 ((SRAM_FRWA_232 << 24) | (SRAM_FRWD_232 <<  8) | \
                                (SRAM_FEA_232  << 16) | (SRAM_FED_232))

    /* SRAM Mac timing (based on 199/232 MHz clock) */

#    define SRAM_MRWA 0x4C /* Mac R/W Assert */
#    define SRAM_MEA  0x52 /* Mac Enable Assert */
#    define SRAM_MRWD 0x0F /* Mac R/W Deassert */
#    define SRAM_MED  0x07 /* Mac Enable Deassert */
#    define SRAM_MAC_CFG ((SRAM_MRWA << 24) | (SRAM_MRWD << 8) | \
                          (SRAM_MEA  << 16) | (SRAM_MED))

    /* SDRAM timing */

#    define SDRAM_RFRSH_200     0x0309 /* Refresh Count */
#    define SDRAM_RFRSH_232     0x038B /* Refresh Count */
#    define SDRAM_BURSTL        0x8    /* Burst Length */
#    define SDRAM_CASL          0x2    /* CAS Latency */
#    define SDRAM_ROW_ADR_WIDTH 0xD    /* Row Address Width */
#    define SDRAM_COL_ADR_WIDTH 0x9    /* Column Address Width */
#    define SDRAM_MEMCTL0_200 ((SDRAM_RFRSH_200 << 16) | (SDRAM_BURSTL << 12) | \
                           (SDRAM_CASL  <<  8) | (SDRAM_ROW_ADR_WIDTH << 4)   | \
                           (SDRAM_COL_ADR_WIDTH))
#    define SDRAM_MEMCTL0_232 ((SDRAM_RFRSH_232 << 16) | (SDRAM_BURSTL << 12) | \
                           (SDRAM_CASL  <<  8) | (SDRAM_ROW_ADR_WIDTH << 4)   | \
                           (SDRAM_COL_ADR_WIDTH))


#    define SDRAM_TRWT_200     0x1 /* Read/Write turnaround time */
#    define SDRAM_TDPL_200     0x2 /* Data In to Precharge time */
#    define SDRAM_TDQZ_200     0x3 /* DQM Data Out Disable latency */
#    define SDRAM_TRC_200      0x6 /* Bank Cycle time */
#    define SDRAM_TRRD_200     0x1 /* Bank to Bank delay time */
#    define SDRAM_TRCD_200     0x1 /* RAS to CAS delay */
#    define SDRAM_TRASMIN_200  0x4 /* Active Command Period */
#    define SDRAM_TRP_200      0x1 /* Precharge Time */

#    define SDRAM_TRWT_232     0x1 /* Read/Write turnaround time */
#    define SDRAM_TDPL_232     0x2 /* Data In to Precharge time */
#    define SDRAM_TDQZ_232     0x3 /* DQM Data Out Disable latency */
#    define SDRAM_TRC_232      0x8 /* Bank Cycle time */
#    define SDRAM_TRRD_232     0x2 /* Bank to Bank delay time */
#    define SDRAM_TRCD_232     0x2 /* RAS to CAS delay */
#    define SDRAM_TRASMIN_232  0x5 /* Active Command Period */
#    define SDRAM_TRP_232      0x2 /* Precharge Time */

#    define SDRAM_MEMCTL1_200 ((SDRAM_TRWT_200 << 28) | (SDRAM_TDPL_200 << 24) |\
                           (SDRAM_TDQZ_200 << 20) | (SDRAM_TRC_200  << 16) | \
                           (SDRAM_TRRD_200 << 12) | (SDRAM_TRCD_200 <<  8) | \
                           (SDRAM_TRASMIN_200 << 4) | (SDRAM_TRP_200))
#    define SDRAM_MEMCTL1_232 ((SDRAM_TRWT_232 << 28) | (SDRAM_TDPL_232 << 24) |\
                           (SDRAM_TDQZ_232 << 20) | (SDRAM_TRC_232  << 16) | \
                           (SDRAM_TRRD_232 << 12) | (SDRAM_TRCD_232 <<  8) | \
                           (SDRAM_TRASMIN_232 << 4) | (SDRAM_TRP_232))

#    define SDRAM_TRSC       0x1     /* Mode register set delay */
#    define SDRAM_INIT_RFRSH 0x2     /* Initialization Refresh Count */
#    define SDRAM_INIT_DLY_200   0x26DF  /* Initialization Delay */
#    define SDRAM_INIT_DLY_232   0x2D5F  /* Initialization Delay */
#    define SDRAM_MEMINIT_200 ((SDRAM_TRSC << 20) | (SDRAM_INIT_RFRSH << 16) | \
                               (SDRAM_INIT_DLY_200))
#    define SDRAM_MEMINIT_232 ((SDRAM_TRSC << 20) | (SDRAM_INIT_RFRSH << 16) | \
                               (SDRAM_INIT_DLY_232))


/* SRAM CSR bits */

#define SRAM_RLK  1 /* ?? Read Lock Order Enable */
#define SRAM_RDY  0 /* ?? Slowport RDY enable */
#define SRAM_CFT  0 /* Comand FIFO Test Enable */
#define SRAM_FLWT 0 /* Flowthrough SRAM Enable */
#define SRAM_BKW  0 /* Bank Switch Wait Enable */
#define SRAM_8MF  1 /* 8MB Flash */
#define SRAM_4MF  0 /* 4MB Flash */
#define SRAM_2MF  0 /* 2MB Flash */
/* SRAM_#MSR defined above */
#define SRAM_1MSR 0 /* 1MB SRAM */
#define SRAM_RLAM 0 /* ASB Read Lock Achieved Mask */
#define SRAM_IRQ  0 /* IRQ Enable */
#define SRAM_FIQ  0 /* FIQ Enable */
#define SRAM_RLRS 0 /* ASB Read Lock Retry Achieved Status */
#define SRAM_RLS  0 /* ASB Read Lock Achieved Status */
#define SRAM_CSR ((SRAM_RLK  << 20) | (SRAM_RDY  << 19) | \
                  (SRAM_CFT  << 18) |                     (SRAM_FLWT << 16) | \
                  (SRAM_BKW  << 15) | (SRAM_8MF  << 14) | (SRAM_4MF  << 13) | \
                  (SRAM_2MF  << 12) | (SRAM_8MSR << 11) | (SRAM_4MSR << 10) | \
                  (SRAM_2MSR <<  9) | (SRAM_1MSR <<  8) | (SRAM_RLAM <<  4) | \
                  (SRAM_IRQ  <<  3) | (SRAM_FIQ  <<  2) | (SRAM_RLRS <<  1) | \
                  (SRAM_RLS))


/* SDRAM Config */

#define SDRAM_EN_FTST   0 /* Enable FIFO RAM test */
#define SDRAM_EN_INT    0 /* Enable Parity Interrupt */
#define SDRAM_EN_IRQ    0 /* Select IRQ */
#define SDRAM_EN_FIQ    0 /* Select FIQ */
#define SDRAM_EN_CPE    0 /* Enable StrongARM Core parity error */
#define SDRAM_EN_PCIPE  0 /* Enable PCI parity error */
#define SDRAM_EN_UEPE   0 /* Enable Microengine parity error */
#define SDRAM_GENPAR    0 /* Enable parity generation */
#define SDRAM_EVENPAR   0 /* Generate even parity */
#define SDRAM_TF_BENDN  0 /* 1 = big endian mode */
#define SDRAM_INIT      1 /* Initialize SDRAM unit */
#define SDRAM_CSR ((SDRAM_EN_FTST   << 15) | (SDRAM_EN_INT    << 10) | \
                   (SDRAM_EN_IRQ    <<  9) | (SDRAM_EN_FIQ    <<  8) | \
                   (SDRAM_EN_CPE    <<  6) | (SDRAM_EN_PCIPE  <<  5) | \
                   (SDRAM_EN_UEPE   <<  4) | (SDRAM_GENPAR    <<  3) | \
                   (SDRAM_EVENPAR   <<  2) | (SDRAM_TF_BENDN  <<  1) | \