21555drv.c

vxworks的BSP开发配置文件

/* 21555drv.c - Intel 21555 Non-Transparent Bridge Driver */

/* Copyright 2000 Intel Corp. */

/*
modification history
--------------------
01b,17jul01,jdg  Allow variable bridge configurations
01a,20dec00,jdg  Created
*/

/*
DESCRIPTION
This library provides support for the Intel 21555 Non-transparent Bridge.
*/


/* includes */

#include "vxWorks.h"
#include "config.h"
#include "dllLib.h"
#include "pciIomapLib.h"

#include "21555drv.h"

/* defines */

#define MASK_4K  (~(4 * 1024 - 1))
#define MASK_8K  (~(8 * 1024 - 1))
#define MASK_1M  (~(1 * 1024 * 1024 -1))
#define MASK_2M  (~(2 * 1024 * 1024 -1))
#define PREFETCHABLE (1<<3)


/*
 * At present, we only use bit 15, later we'll also use bit 14 for the
 * second 1200
 */
#define DOORBELL_BITS (1 << 15)


#define REG_READ16(a) (*(volatile UINT16*)(a))
#define REG_WRITE16(a,val) (*(volatile UINT16*)(a)) = (val)

/* imports */


/* typedefs */

typedef struct ntbInfo         /* Non transparent bridge info */
{
    UINT32 ioBase;
} NTB_INFO;


/* globals */

NTB_INFO ntbInfo;


/* locals */


/* forward declarations */


/*******************************************************************************
*
* sysIntel21555PreInit - Initialize 21555 NTB
*
* This routine finds the bridge and initializes it's CSRs.
* It should be called after pciIomapLibInit is called, and before
* PCI addresses are assigned (sysPciAssignAddrs).
*
* RETURNS: OK, or ERROR
*/
STATUS sysIntel21555PreInit
    (
    UINT32 upstreamSize   /* Size of upstream window: 16K - 2G */
    )
{
    UINT32 pciBus;      /* PCI bus number */
    UINT32 pciDevice;   /* PCI device number */
    UINT32 pciFunc;     /* PCI Function number */
    UINT16 data0, data1;
    UINT32 size;

    for (size = 31; size >= 14; size--) {
        if (upstreamSize == (UINT32)(1 << size))
            break;
    }
    if (size < 14)
      {
        return ERROR;
      }

    if (OK != pciFindDevice(INT21555_VEND_ID, INT21555_DEVICE_ID,
                            0, &pciBus, &pciDevice, &pciFunc))
    {
        return ERROR;
    }


    /*
     * Set up Secondary BAR masks and address mapping
     *
     * ADDR REG                  TYPE SIZE   PURPOSE
     * 10   Sec CSR Mem          Mem  N/A    not used
     * 14   Sec CSR              IO   N/A    21555 CSRs
     * 18   Upstream IOM Bar 0   Mem  4K     not used
     * 1C   Upstream Mem Bar 1   Mem  4K     not used
     * 20   Upstream Mem Bar 2   Mem  var    General Primary Access
     */

    pciConfigOutLong(pciBus, pciDevice, pciFunc,
                     PCI_US_IOMEM_0_SETUP, MASK_4K);
    pciConfigOutLong(pciBus, pciDevice, pciFunc,
                     PCI_US_MEM_1_SETUP, MASK_4K);


    /* Program up Upstream Mem 2 size */
    pciConfigInWord(pciBus, pciDevice, pciFunc,
                    PCI_CHIP_CTRL_0,
                    &data0);
    pciConfigInWord(pciBus, pciDevice, pciFunc,
                    PCI_CHIP_CTRL_1,
                    &data1);

    data1 &= ~0x0F00;
    if (size >= 29) {
        data0 |= 0x1000;
        data1 |= (size - 28) << 8;
    } else {
        data0 &= ~0x1000;
        data1 |= (size - 13) << 8;
    }

    pciConfigOutWord(pciBus, pciDevice, pciFunc,
                     PCI_CHIP_CTRL_0,
                     data0);
    pciConfigOutWord(pciBus, pciDevice, pciFunc,
                     PCI_CHIP_CTRL_1,
                     data1);

    return OK;
}



/*******************************************************************************
*
* readCsrIoBase - Reads the CSR IO Base after PCI address assignments
*
* This routine finds the bridge and reads the CSR IO Base
*
* RETURNS: OK, or ERROR
*/
STATUS readCsrIoBase
    (
    )
{
    UINT32 pciBus;      /* PCI bus number */
    UINT32 pciDevice;   /* PCI device number */
    UINT32 pciFunc;     /* PCI Function number */

    if (OK != pciFindDevice(INT21555_VEND_ID, INT21555_DEVICE_ID,
                            0, &pciBus, &pciDevice, &pciFunc))
    {
        return ERROR;
    }


    /* Read CSR IO Base */

    pciConfigInLong(pciBus, pciDevice, pciFunc, PCI_CFG_BASE_ADDRESS_1,
                    &ntbInfo.ioBase); /* CSR IO Base */
    ntbInfo.ioBase &= ~PCI_HEADER_TYPE_MASK;
    ntbInfo.ioBase |= PCI_IO_BASE;

	return OK;
}
	
/*******************************************************************************
*
* sysIntel21555PostInit - Initialize 21555 NTB after PCI address assignments
*
* This routine finds the bridge and does any initialization that needs to
* occur after PCI addresses are assigned (sysPciAssignAddrs).
*
* RETURNS: OK, or ERROR
*/
STATUS sysIntel21555PostInit
    (
    short vendId,             /* Subsystem Vendor ID */
    short sysId,              /* Subsystem ID */
    UINT32 sdramWindowSize,   /* Size of SDRAM Window in Pri PCI */
    UINT32 sdramWindowOffset  /* Offset of window from start of SDram */
    )
{
    UINT32 pciBus;      /* PCI bus number */
    UINT32 pciDevice;   /* PCI device number */
    UINT32 pciFunc;     /* PCI Function number */
    UINT32 addr;
    UINT16 data;

    if (OK != pciFindDevice(INT21555_VEND_ID, INT21555_DEVICE_ID,
                            0, &pciBus, &pciDevice, &pciFunc))
    {
        return ERROR;
    }


    /* Read CSR IO Base */

    pciConfigInLong(pciBus, pciDevice, pciFunc, PCI_CFG_BASE_ADDRESS_1,
                    &ntbInfo.ioBase); /* CSR IO Base */
    ntbInfo.ioBase &= ~PCI_HEADER_TYPE_MASK;
    ntbInfo.ioBase |= PCI_IO_BASE;


    /* Set Subsystem ID */
    pciConfigOutWord(pciBus, pciDevice, pciFunc, PCI_CFG_SUB_VENDER_ID,
                     vendId);
    pciConfigOutWord(pciBus, pciDevice, pciFunc, PCI_CFG_SUB_SYSTEM_ID,
                     sysId);

    /*
     * Set up primary BAR masks and address mapping
     *
     * ADDR REG                  TYPE SIZE   PURPOSE
     * 10   Pri CSR / DS Mem 0   Mem  4K     not used
     * 14   Pri CSR              IO   N/A    21555 CSRs
     * 18   Downstream IOM Bar 1 Mem  1(2)M  MEM/CSR 0/1 (1200's CSRs)
     * 1C   Downstream Mem Bar 2 Mem  var    MEM 0 (1200's SDRAM)
     * 20   Downstream Mem Bar 3 Mem  var    MEM 1 (unused at present)
     */

    pciConfigOutLong(pciBus, pciDevice, pciFunc,
                     PCI_DS_MEM_0_SETUP, MASK_4K);
    pciConfigOutLong(pciBus, pciDevice, pciFunc,
                     PCI_DS_IOMEM_1_SETUP, MASK_1M);
    pciConfigOutLong(pciBus, pciDevice, pciFunc,
                     PCI_DS_MEM_2_SETUP, ~(sdramWindowSize-1) | PREFETCHABLE);
    pciConfigOutLong(pciBus, pciDevice, pciFunc,
                     PCI_DS_MEM_3_SETUP, 0);


    /* IOMEM_1 is set to point to our CSR MEM base */
    addr = *(UINT32 *) (IXM1200_PCI_MEM_BAR);
    pciConfigOutLong(pciBus, pciDevice, pciFunc,
                     PCI_DS_IOMEM_1_TBASE, addr);


    pciConfigOutLong(pciBus, pciDevice, pciFunc,
                     PCI_DS_MEM_2_TBASE, sdramWindowOffset);

    /* Set secondary PCI command reg to allow transactions */
    pciConfigOutWord(pciBus, pciDevice, pciFunc,
                     PCI_CFG_COMMAND,
                     PCI_CMD_IO_ENABLE |
                     PCI_CMD_MEM_ENABLE |
                     PCI_CMD_MASTER_ENABLE);

    /* Allow primary PCI to do config cycles */
    pciConfigInWord(pciBus, pciDevice, pciFunc,
                    PCI_CHIP_CTRL_0,
                    &data);
    data &= ~(PCI_CHIP_C0_PR_ACC_LOCK);
    pciConfigOutWord(pciBus, pciDevice, pciFunc,
                     PCI_CHIP_CTRL_0,
                     data);

    /* Program Doorbell register */
    /* Clear interrupt request */
    REG_WRITE16(ntbInfo.ioBase + PCI_PRI_CLR_IRQ, DOORBELL_BITS);
    /* Enable doorbell */
    REG_WRITE16(ntbInfo.ioBase + PCI_PRI_CLR_IRQ_MASK, DOORBELL_BITS);

    return OK;
}

/*******************************************************************************
*
* sysGet21555DBAddr - Get 21555 doorbell set address
*
* This routine returns the address of the 21555 doorbell set register
*
* RETURNS: Address
*/
UINT32 sysGet21555DBAddr ()
{
    return (ntbInfo.ioBase + PCI_PRI_SET_IRQ);
}